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authorJoonyoung Shim <jy0922.shim@samsung.com>2018-09-24 13:00:56 +0200
committerSylwester Nawrocki <snawrocki@kernel.org>2018-10-05 13:36:37 +0200
commitd32dd2a1a0f80edad158c9a1ba5f47650d9504a0 (patch)
tree871e2aa17a3d0d7165a54725147d52965ae5fd16 /drivers/clk/samsung
parentclk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend (diff)
downloadlinux-d32dd2a1a0f80edad158c9a1ba5f47650d9504a0.tar.xz
linux-d32dd2a1a0f80edad158c9a1ba5f47650d9504a0.zip
clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to handle the bit only on exynos5420. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> [m.szyprow: rewrote commit subject] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 76e7686c6162..a2d6e7f4bcd3 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -568,6 +568,7 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
};
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
+ GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
};
@@ -1097,8 +1098,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
- GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
-
/* GEN Block */
GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),