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authorMarian Mihailescu <mihailescu2m@gmail.com>2019-10-29 01:50:25 +0100
committerSylwester Nawrocki <s.nawrocki@samsung.com>2019-10-29 11:31:36 +0100
commite21be0d1d7bd7f78a77613f6bcb6965e72b22fc1 (patch)
treecdd813d9a4eb310b39e7ecea26f57d3980281baa /drivers/clk/samsung
parentclk: samsung: exynos5420: Add VPLL rate table (diff)
downloadlinux-e21be0d1d7bd7f78a77613f6bcb6965e72b22fc1.tar.xz
linux-e21be0d1d7bd7f78a77613f6bcb6965e72b22fc1.zip
clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
Save and restore top PLL related configuration registers for big (APLL) and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks were reset to default values after suspend/resume cycle and performance after system resume was affected when performance governor has been selected. Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list") Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index bbd7baab0899..53bbd656a3f6 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -165,6 +165,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
GATE_BUS_CPU,
GATE_SCLK_CPU,
CLKOUT_CMU_CPU,
+ APLL_CON0,
+ KPLL_CON0,
CPLL_CON0,
DPLL_CON0,
EPLL_CON0,