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authorMaxime Ripard <maxime@cerno.tech>2021-05-11 13:35:52 +0200
committerMaxime Ripard <maxime@cerno.tech>2021-05-11 13:35:52 +0200
commitc55b44c9386f3ee1b08752638559f19deaf6040d (patch)
treec843a21f45180387fcd9eb2625cc9d1f166a3156 /drivers/clk/socfpga/clk-s10.c
parentMAINTAINERS: Update my e-mail (diff)
parentLinux 5.13-rc1 (diff)
downloadlinux-c55b44c9386f3ee1b08752638559f19deaf6040d.tar.xz
linux-c55b44c9386f3ee1b08752638559f19deaf6040d.zip
Merge drm/drm-fixes into drm-misc-fixes
Start this new release drm-misc-fixes branch Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers/clk/socfpga/clk-s10.c')
-rw-r--r--drivers/clk/socfpga/clk-s10.c68
1 files changed, 29 insertions, 39 deletions
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index 661a8e9bfb9b..f0bd77138ecb 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -274,18 +274,18 @@ static const struct stratix10_gate_clock s10_gate_clks[] = {
static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
int nums, struct stratix10_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_periph(&clks[i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_periph(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
@@ -293,18 +293,18 @@ static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
int nums, struct stratix10_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_cnt_periph(&clks[i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_cnt_periph(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
@@ -313,18 +313,18 @@ static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *cl
static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
int nums, struct stratix10_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_gate(&clks[i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_gate(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
@@ -333,62 +333,50 @@ static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
int nums, struct stratix10_clock_data *data)
{
- struct clk *clk;
+ struct clk_hw *hw_clk;
void __iomem *base = data->base;
int i;
for (i = 0; i < nums; i++) {
- clk = s10_register_pll(&clks[i], base);
- if (IS_ERR(clk)) {
+ hw_clk = s10_register_pll(&clks[i], base);
+ if (IS_ERR(hw_clk)) {
pr_err("%s: failed to register clock %s\n",
__func__, clks[i].name);
continue;
}
- data->clk_data.clks[clks[i].id] = clk;
+ data->clk_data.hws[clks[i].id] = hw_clk;
}
return 0;
}
-static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev,
- int nr_clks)
+static int s10_clkmgr_init(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct stratix10_clock_data *clk_data;
- struct clk **clk_table;
struct resource *res;
void __iomem *base;
+ int i, num_clks;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base)) {
pr_err("%s: failed to map clock registers\n", __func__);
- return ERR_CAST(base);
+ return PTR_ERR(base);
}
- clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
+ num_clks = STRATIX10_NUM_CLKS;
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
+ num_clks), GFP_KERNEL);
if (!clk_data)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
- clk_data->base = base;
- clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
- if (!clk_table)
- return ERR_PTR(-ENOMEM);
-
- clk_data->clk_data.clks = clk_table;
- clk_data->clk_data.clk_num = nr_clks;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
- return clk_data;
-}
+ for (i = 0; i < num_clks; i++)
+ clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
-static int s10_clkmgr_init(struct platform_device *pdev)
-{
- struct stratix10_clock_data *clk_data;
-
- clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS);
- if (IS_ERR(clk_data))
- return PTR_ERR(clk_data);
+ clk_data->base = base;
+ clk_data->clk_data.num = num_clks;
s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
@@ -401,6 +389,8 @@ static int s10_clkmgr_init(struct platform_device *pdev)
s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
clk_data);
+
+ of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
return 0;
}