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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-15 00:02:15 +0100 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2022-12-07 13:22:37 +0100 |
| commit | ef87bd81cb881377c1eaf512167b0522c825b012 (patch) | |
| tree | 47be039c443d7dbfb8363dfbc1efd3d8e56f3d19 /drivers/clk/socfpga/clk.h | |
| parent | dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" (diff) | |
| download | linux-ef87bd81cb881377c1eaf512167b0522c825b012.tar.xz linux-ef87bd81cb881377c1eaf512167b0522c825b012.zip | |
mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase
The clock-phase settings for the SDMMC controller in the SoCFPGA
platforms reside in a register in the System Manager. Add a method
to access that register through the syscon interface.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20221114230217.202634-4-dinguyen@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/clk/socfpga/clk.h')
0 files changed, 0 insertions, 0 deletions