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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-03-23 17:38:26 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-04-22 00:29:23 +0200 |
| commit | fa4d0ca104bfdcda7b7e2bac855b358f302fd310 (patch) | |
| tree | 14c68c6b45413a4281a7d53af3b84564400a4bf1 /drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | |
| parent | dt-bindings: clk: sun5i: add DRAM gates compatible (diff) | |
| download | linux-fa4d0ca104bfdcda7b7e2bac855b358f302fd310.tar.xz linux-fa4d0ca104bfdcda7b7e2bac855b358f302fd310.zip | |
clk: sunxi: Add PLL3 clock
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi/clk-sun4i-tcon-ch1.c')
0 files changed, 0 insertions, 0 deletions