diff options
| author | Thierry Reding <treding@nvidia.com> | 2015-04-08 16:48:26 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2016-04-28 12:41:46 +0200 |
| commit | 07314fc108e195044c074f4b443974b5aaa2d5d7 (patch) | |
| tree | 0a35cd6f1464968b08f384ed6d4ab093a31f4d5f /drivers/clk/tegra/clk-tegra114.c | |
| parent | clk: tegra: Remove trailing blank line (diff) | |
| download | linux-07314fc108e195044c074f4b443974b5aaa2d5d7.tar.xz linux-07314fc108e195044c074f4b443974b5aaa2d5d7.zip | |
clk: tegra: Special-case mipi-cal parent on Tegra114
Starting with Tegra124, the mipi-cal clock uses the 72 MHz clock as its
source. On Tegra114 this clock's parent was clk_m, so it is the one-off
chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index df47ec3169c3..b78054fac0a8 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -743,7 +743,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true }, [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true }, [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true }, - [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true }, [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true }, [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true }, [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true }, @@ -1237,6 +1236,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base, &emc_lock); clks[TEGRA114_CLK_MC] = clk; + clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, + CLK_SET_RATE_PARENT, 56, + periph_clk_enb_refcnt); + clks[TEGRA114_CLK_MIPI_CAL] = clk; + for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { data = &tegra_periph_clk_list[i]; clk = tegra_clk_register_periph(data->name, |