diff options
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2020-01-14 08:24:27 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-03-12 12:10:49 +0100 |
| commit | efdd205ccbfaa80bd932bc2fba498026c09db502 (patch) | |
| tree | 82748d78c6494b61e60c3611252f03764d4ad942 /drivers/clk/tegra/clk-tegra114.c | |
| parent | clk: tegra: Remove tegra_pmc_clk_init along with clk ids (diff) | |
| download | linux-efdd205ccbfaa80bd932bc2fba498026c09db502.tar.xz linux-efdd205ccbfaa80bd932bc2fba498026c09db502.zip | |
clk: tegra: Remove audio clocks configuration from clock driver
Current clock driver enables PLLA, cdev1 on Tegra20 and extern1 on
Tegra30 and above as a part of clocks init and there is no need to
have these audio clocks enabled by the clock driver.
extern1 is used as parent for clk_out_1 and clk_out_1 is dedicated
for audio mclk on Tegra30 and above Tegra platforms and these clocks
are taken care by ASoC driver.
So, this patch removes audio related clocks configuration from clock
init of Tegra20 and above.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra114.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index c138ef75480b..bc9e47a4cb60 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1136,9 +1136,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 }, { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 }, { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 }, - { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 }, - { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 }, - { TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 }, + { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 }, + { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 }, { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 }, |