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authorLaxman Dewangan <ldewangan@nvidia.com>2013-02-12 16:17:59 +0100
committerStephen Warren <swarren@nvidia.com>2013-02-13 19:17:03 +0100
commit527fad1bc519df8eedd397482febb51526e5d987 (patch)
tree003feaff3289f9d27292d2332710e951f142ea25 /drivers/clk/tegra/clk-tegra30.c
parentARM: tegra: remove clock-frequency properties from serial nodes (diff)
downloadlinux-527fad1bc519df8eedd397482febb51526e5d987.tar.xz
linux-527fad1bc519df8eedd397482febb51526e5d987.zip
clk: tegra: initialise parent of uart clocks
Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
-rw-r--r--drivers/clk/tegra/clk-tegra30.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index bfe3dd4fe847..32c61cb6d0bb 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1877,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
};
static __initdata struct tegra_clk_init_table init_table[] = {
- {uarta, pll_p, 408000000, 1},
+ {uarta, pll_p, 408000000, 0},
+ {uartb, pll_p, 408000000, 0},
+ {uartc, pll_p, 408000000, 0},
+ {uartd, pll_p, 408000000, 0},
+ {uarte, pll_p, 408000000, 0},
{pll_a, clk_max, 564480000, 1},
{pll_a_out0, clk_max, 11289600, 1},
{extern1, pll_a_out0, 0, 1},