diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-02-28 15:37:22 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-03-20 14:07:48 +0100 |
| commit | 24c3ebef1ab6d5620eaaa51f69223118cac97db6 (patch) | |
| tree | cbeb8fe67d558a7e2986caee5089c4691e6d65af /drivers/clk/tegra | |
| parent | clk: tegra: Add super clock mux/divider (diff) | |
| download | linux-24c3ebef1ab6d5620eaaa51f69223118cac97db6.tar.xz linux-24c3ebef1ab6d5620eaaa51f69223118cac97db6.zip | |
clk: tegra: Add aclk
This clock clocks the ADSP Cortex-A9.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index cfe70781e2b4..9a2512a6b419 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2308,6 +2308,11 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = { static struct clk **clks; +static const char * const aclk_parents[] = { + "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3", + "clk_m" +}; + static __init void tegra210_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base) { @@ -2369,6 +2374,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, clk_register_clkdev(clk, "cml1", NULL); clks[TEGRA210_CLK_CML1] = clk; + clk = tegra_clk_register_super_clk("aclk", aclk_parents, + ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, + 0, NULL); + clks[TEGRA210_CLK_ACLK] = clk; + tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); } |