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| author | Michael Turquette <mturquette@baylibre.com> | 2017-04-12 18:51:01 +0200 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2017-04-12 18:51:01 +0200 |
| commit | 72be2d5f4aa4134ae284108d319adf42f1739816 (patch) | |
| tree | c9cae918b467dc5740dfff3e718595db632bc65c /drivers/clk/zte | |
| parent | cs-2000-cp: keep Reserved bit on each register (diff) | |
| parent | clk: tegra: Don't reset PLL-CX if it is already enabled (diff) | |
| download | linux-72be2d5f4aa4134ae284108d319adf42f1739816.tar.xz linux-72be2d5f4aa4134ae284108d319adf42f1739816.zip | |
Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
Pull Tegra clk driver updates from Thierry Reding:
This contains a bunch of fixes and cleanups, mostly to the Tegra210
clock driver.
* tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits)
clk: tegra: Don't reset PLL-CX if it is already enabled
clk: tegra: Add missing Tegra210 clocks
clk: tegra: Propagate clk_out_x rate to parent
clk: tegra: Fix build warnings on Tegra20/Tegra30
clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
clk: tegra: Add SATA seq input control
clk: tegra: Add Tegra210 special resets
clk: tegra: Rework pll_u
clk: tegra: Implement reset control reset
clk: tegra: Fix disable unused for clocks sharing enable bit
clk: tegra: Handle UTMIPLL IDDQ
clk: tegra: Add aclk
clk: tegra: Add super clock mux/divider
clk: tegra: Define Tegra210 DMIC clocks
clk: tegra: Fix constness for peripheral clocks
clk: tegra: Define Tegra210 DMIC sync clocks
clk: tegra: Add CEC clock
clk: tegra: Fix type for m field
clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation
clk: tegra: Don't warn for PLL defaults unnecessarily
...
Diffstat (limited to 'drivers/clk/zte')
0 files changed, 0 insertions, 0 deletions