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| author | Chukun Pan <amadeus@jmu.edu.cn> | 2024-06-20 17:01:21 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-06-26 06:03:47 +0200 |
| commit | f2743ae3ff84579981ac513f512b9df945d109c0 (patch) | |
| tree | 5347e49170122c4e9b8b34f6b535f030e43a6efc /drivers/clk | |
| parent | Merge branch '20240602114439.1611-1-quic_jkona@quicinc.com' into clk-for-6.11 (diff) | |
| download | linux-f2743ae3ff84579981ac513f512b9df945d109c0.tar.xz linux-f2743ae3ff84579981ac513f512b9df945d109c0.zip | |
clk: qcom: gcc-ipq6018: update sdcc max clock frequency
The mmc controller of the IPQ6018 does not support HS400 mode.
So adjust the maximum clock frequency of sdcc to 200 MHz (HS200).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20240620150122.1406631-2-amadeus@jmu.edu.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq6018.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 9e5885101366..2e411d874662 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -1617,7 +1617,7 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { F(96000000, P_GPLL2, 12, 0, 0), F(177777778, P_GPLL0, 4.5, 0, 0), F(192000000, P_GPLL2, 6, 0, 0), - F(384000000, P_GPLL2, 3, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), { } }; |