diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-03-23 09:50:07 +0100 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-04-12 20:32:56 +0200 |
| commit | fa5ad5c51706e5407a3bb56c9542a63c81e35a2f (patch) | |
| tree | c2268a9bb495788fe5b8964845468dba516eee7e /drivers/clk | |
| parent | clk: qcom: regmap-mux: add pipe clk implementation (diff) | |
| download | linux-fa5ad5c51706e5407a3bb56c9542a63c81e35a2f.tar.xz linux-fa5ad5c51706e5407a3bb56c9542a63c81e35a2f.zip | |
clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks
Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let
the clock framework automatically park the clock when the clock is
switched off and restore the parent when the clock is switched on.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220323085010.1753493-3-dmitry.baryshkov@linaro.org
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-sm8450.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 593a195467ff..fb6decd3df49 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -243,13 +243,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { .reg = 0x7b060, .shift = 0, .width = 2, + .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_4, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk_src", .parent_data = gcc_parent_data_4, .num_parents = ARRAY_SIZE(gcc_parent_data_4), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; @@ -273,13 +274,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { .reg = 0x9d064, .shift = 0, .width = 2, + .safe_src_parent = P_BI_TCXO, .parent_map = gcc_parent_map_6, .clkr = { .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_1_pipe_clk_src", .parent_data = gcc_parent_data_6, .num_parents = ARRAY_SIZE(gcc_parent_data_6), - .ops = &clk_regmap_mux_closest_ops, + .ops = &clk_regmap_mux_safe_ops, }, }, }; |