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| author | Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com> | 2024-10-23 12:21:10 +0200 |
|---|---|---|
| committer | Mario Limonciello <mario.limonciello@amd.com> | 2024-10-28 20:54:36 +0100 |
| commit | 796ff50e127af8362035f87ba29b6b84e2dd9742 (patch) | |
| tree | 3bdbcb98b3d01a3c39a5ce911303591da8f13514 /drivers/cpufreq/amd-pstate.c | |
| parent | cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE (diff) | |
| download | linux-796ff50e127af8362035f87ba29b6b84e2dd9742.tar.xz linux-796ff50e127af8362035f87ba29b6b84e2dd9742.zip | |
cpufreq/amd-pstate: Call cppc_set_epp_perf in the reenable function
The EPP value being set in perf_ctrls.energy_perf is not being propagated
to the shared memory, fix that.
Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Perry Yuan <perry.yuan@amd.com>
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Link: https://lore.kernel.org/r/20241023102108.5980-4-Dhananjay.Ugwekar@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Diffstat (limited to 'drivers/cpufreq/amd-pstate.c')
| -rw-r--r-- | drivers/cpufreq/amd-pstate.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 576251e61ce0..bbeddce90823 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1616,8 +1616,9 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.max_perf = max_perf; - perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached); cppc_set_perf(cpudata->cpu, &perf_ctrls); + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached); + cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); } } @@ -1658,8 +1659,9 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) } else { perf_ctrls.desired_perf = 0; perf_ctrls.max_perf = min_perf; - perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE); cppc_set_perf(cpudata->cpu, &perf_ctrls); + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE); + cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); } mutex_unlock(&amd_pstate_limits_lock); } |