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authorHui Tang <tanghui20@huawei.com>2021-01-18 09:18:19 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2021-01-29 05:57:58 +0100
commitbc005983e88ac45a284f70dd6ce5707a0c9dddc4 (patch)
tree4f5bf272579ea24d9d89ea7fccfceffb03a71226 /drivers/crypto/hisilicon/hpre/hpre_main.c
parentcrypto: hisilicon/hpre - add two RAS correctable errors processing (diff)
downloadlinux-bc005983e88ac45a284f70dd6ce5707a0c9dddc4.tar.xz
linux-bc005983e88ac45a284f70dd6ce5707a0c9dddc4.zip
crypto: hisilicon/hpre - add ecc algorithm inqury for uacce device
Uacce SysFS support more algorithms inqury such as 'ecdh/ecdsa/sm2/x25519/x448' Signed-off-by: Hui Tang <tanghui20@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/hisilicon/hpre/hpre_main.c')
-rw-r--r--drivers/crypto/hisilicon/hpre/hpre_main.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c b/drivers/crypto/hisilicon/hpre/hpre_main.c
index d46086e1b922..3b3481e7527c 100644
--- a/drivers/crypto/hisilicon/hpre/hpre_main.c
+++ b/drivers/crypto/hisilicon/hpre/hpre_main.c
@@ -778,7 +778,10 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
return -EINVAL;
}
- qm->algs = "rsa\ndh\n";
+ if (pdev->revision >= QM_HW_V3)
+ qm->algs = "rsa\ndh\necdh\nx25519\nx448\necdsa\nsm2\n";
+ else
+ qm->algs = "rsa\ndh\n";
qm->mode = uacce_mode;
qm->pdev = pdev;
qm->ver = pdev->revision;