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authorDan Williams <dan.j.williams@intel.com>2023-06-26 03:56:13 +0200
committerDan Williams <dan.j.williams@intel.com>2023-06-26 03:56:13 +0200
commit0c0df63177e37ae826d803280eb2c5b6b6a7a9a4 (patch)
tree5b158934251cb6537491371d3dd09fcf349a3102 /drivers/cxl/cxlmem.h
parentMerge branch 'for-6.5/cxl-perf' into for-6.5/cxl (diff)
parentcxl/port: Store the downstream port's Component Register mappings in struct c... (diff)
downloadlinux-0c0df63177e37ae826d803280eb2c5b6b6a7a9a4.tar.xz
linux-0c0df63177e37ae826d803280eb2c5b6b6a7a9a4.zip
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Pick up the first half of the RCH error handling series. The back half needs some fixups for test regressions. Small conflicts with the PMU work around register enumeration and setup helpers.
Diffstat (limited to 'drivers/cxl/cxlmem.h')
-rw-r--r--drivers/cxl/cxlmem.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 25234a491371..79e99c873ca2 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -75,13 +75,13 @@ cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
{
struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
- return to_cxl_memdev(port->uport);
+ return to_cxl_memdev(port->uport_dev);
}
bool is_cxl_memdev(const struct device *dev);
static inline bool is_cxl_endpoint(struct cxl_port *port)
{
- return is_cxl_memdev(port->uport);
+ return is_cxl_memdev(port->uport_dev);
}
struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);