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| author | Felix Kuehling <Felix.Kuehling@amd.com> | 2019-08-30 03:18:43 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-09-14 00:36:08 +0200 |
| commit | 17da41bf00c849d809cb3cc5eebc43a1924736fd (patch) | |
| tree | 61b7419114c617b915c078a358e04fb8342f442c /drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | |
| parent | drm/amdgpu: Use optimal mtypes and PTE bits for Arcturus (diff) | |
| download | linux-17da41bf00c849d809cb3cc5eebc43a1924736fd.tar.xz linux-17da41bf00c849d809cb3cc5eebc43a1924736fd.zip | |
drm/amdgpu: Remove unnecessary TLB workaround (v2)
This workaround is better handled in user mode in a way that doesn't
require allocating extra memory and breaking userptr BOs.
The TLB bug is a performance bug, not a functional or security bug.
Hence it is safe to remove this kernel part of the workaround to
allow a better workaround using only virtual address alignments in
user mode.
v2: Removed VI_BO_SIZE_ALIGN definition
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f8328e069d94..55fce91f7fb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -33,11 +33,6 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" -/* Special VM and GART address alignment needed for VI pre-Fiji due to - * a HW bug. - */ -#define VI_BO_SIZE_ALIGN (0x8000) - /* BO flag to indicate a KFD userptr BO */ #define AMDGPU_AMDKFD_USERPTR_BO (1ULL << 63) @@ -1111,7 +1106,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( uint64_t user_addr = 0; struct amdgpu_bo *bo; struct amdgpu_bo_param bp; - int byte_align; u32 domain, alloc_domain; u64 alloc_flags; int ret; @@ -1166,15 +1160,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if ((*mem)->aql_queue) size = size >> 1; - /* Workaround for TLB bug on older VI chips */ - byte_align = (adev->family == AMDGPU_FAMILY_VI && - adev->asic_type != CHIP_FIJI && - adev->asic_type != CHIP_POLARIS10 && - adev->asic_type != CHIP_POLARIS11 && - adev->asic_type != CHIP_POLARIS12 && - adev->asic_type != CHIP_VEGAM) ? - VI_BO_SIZE_ALIGN : 1; - (*mem)->alloc_flags = flags; amdgpu_sync_create(&(*mem)->sync); @@ -1190,7 +1175,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( memset(&bp, 0, sizeof(bp)); bp.size = size; - bp.byte_align = byte_align; + bp.byte_align = 1; bp.domain = alloc_domain; bp.flags = alloc_flags; bp.type = bo_type; |