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| author | Huang Rui <ray.huang@amd.com> | 2017-05-31 15:52:00 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-06-06 22:58:16 +0200 |
| commit | d5c87390f1a0e82c3ce4ab8d7ba8a323e8729484 (patch) | |
| tree | e9105d4119c841ae4e59ac550ae2327ff95609b5 /drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | |
| parent | drm/amdgpu: abstract system domain enablement for gfxhub/mmhub (diff) | |
| download | linux-d5c87390f1a0e82c3ce4ab8d7ba8a323e8729484.tar.xz linux-d5c87390f1a0e82c3ce4ab8d7ba8a323e8729484.zip | |
drm/amdgpu: abstract disable identity aperture for gfxhub/mmhub
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 36 |
1 files changed, 20 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c index 261416165fdf..bd0542511327 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c @@ -186,6 +186,25 @@ static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL), tmp); } +static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) +{ + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), + 0XFFFFFFFF); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); + + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); + WREG32(SOC15_REG_OFFSET(MMHUB, 0, + mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); +} + int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) { u32 tmp; @@ -210,22 +229,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) mmhub_v1_0_init_cache_regs(adev); mmhub_v1_0_enable_system_domain(adev); - - /* Disable identity aperture.*/ - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); - - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); - - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); - WREG32(SOC15_REG_OFFSET(MMHUB, 0, - mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); + mmhub_v1_0_disable_identity_aperture(adev); for (i = 0; i <= 14; i++) { tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) |