diff options
author | Yifan Zhang <yifan1.zhang@amd.com> | 2022-01-21 11:40:39 +0100 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2022-02-18 20:07:00 +0100 |
commit | 935ad3a74c7d231b82e7fca15899a5cab4195b95 (patch) | |
tree | fbb02d6d61a43b2e58dc1fda4de3501588c20bea /drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | |
parent | drm/amdgpu: enable vcn pg and cg for vcn 3.1.2 (diff) | |
download | linux-935ad3a74c7d231b82e7fca15899a5cab4195b95.tar.xz linux-935ad3a74c7d231b82e7fca15899a5cab4195b95.zip |
drm/amdgpu: add support for nbio 7.3.0
this patch adds support for nbio 7.3.0.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c index 44f17bbfeb6a..6f81de6f3cc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c @@ -61,6 +61,7 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) switch (adev->ip_versions[NBIO_HWIP][0]) { case IP_VERSION(7, 2, 1): + case IP_VERSION(7, 3, 0): case IP_VERSION(7, 5, 0): tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC); break; @@ -79,6 +80,7 @@ static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable) { switch (adev->ip_versions[NBIO_HWIP][0]) { case IP_VERSION(7, 2, 1): + case IP_VERSION(7, 3, 0): case IP_VERSION(7, 5, 0): if (enable) WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, @@ -262,6 +264,7 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev switch (adev->ip_versions[NBIO_HWIP][0]) { case IP_VERSION(7, 2, 1): + case IP_VERSION(7, 3, 0): case IP_VERSION(7, 5, 0): def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) @@ -368,6 +371,7 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) uint32_t def, data; switch (adev->ip_versions[NBIO_HWIP][0]) { case IP_VERSION(7, 2, 1): + case IP_VERSION(7, 3, 0): case IP_VERSION(7, 5, 0): def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3)); data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3, |