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author | Le Ma <le.ma@amd.com> | 2021-11-17 09:28:51 +0100 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2023-04-18 22:28:55 +0200 |
commit | 5aa998baab3360d0f1b93d6aff3df924045f956c (patch) | |
tree | 12560b2ea0f791163cc6fb93aeb858f6ded72802 /drivers/gpu/drm/amd/amdgpu/soc15.h | |
parent | drm/amdgpu: split gc v9_4_3 functionality from gc v9_0 (diff) | |
download | linux-5aa998baab3360d0f1b93d6aff3df924045f956c.tar.xz linux-5aa998baab3360d0f1b93d6aff3df924045f956c.zip |
drm/amdgpu: add xcc index argument to soc15_grbm_select
To support grbm select for multiple XCD case.
v2: unify naming style
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.h')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index efc2a253e8db..2b41ee968dd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -100,7 +100,7 @@ struct soc15_ras_field_entry { #define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift) void soc15_grbm_select(struct amdgpu_device *adev, - u32 me, u32 pipe, u32 queue, u32 vmid); + u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id); void soc15_set_virt_ops(struct amdgpu_device *adev); void soc15_program_register_sequence(struct amdgpu_device *adev, |