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authorXiaojian Du <Xiaojian.Du@amd.com>2020-10-30 09:10:09 +0100
committerAlex Deucher <alexander.deucher@amd.com>2020-11-13 06:12:51 +0100
commit349a32898838a4b9b78d6258fe8b20c60029438d (patch)
tree1b0e8d5e2a4f69d2a3d8105bcfdd318457f4ce62 /drivers/gpu/drm/amd/pm/inc
parentdrm/amd/pm: add the interface to dump smu metrics table for vangogh (diff)
downloadlinux-349a32898838a4b9b78d6258fe8b20c60029438d.tar.xz
linux-349a32898838a4b9b78d6258fe8b20c60029438d.zip
drm/amd/pm: update the swSMU headers for vangogh
This patch is to update the swSMU headers for vangogh. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/inc')
-rw-r--r--drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h6
-rw-r--r--drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h11
-rw-r--r--drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h11
3 files changed, 22 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
index 8f438c80132e..1c19eae93ff1 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -142,6 +142,12 @@ typedef struct {
uint8_t NumDfPstatesEnabled;
uint8_t NumDpmLevelsEnabled;
+ uint8_t NumDcfclkLevelsEnabled;
+ uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk
+ uint8_t NumSocClkLevelsEnabled;
+
+ uint8_t IspClkLevelsEnabled; //applies to both ispiclk and ispxclk
+ uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
uint8_t spare[2];
} DpmClocks_t;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
index 99a406984135..22edd88b8117 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -90,14 +90,16 @@
#define FEATURE_ATHUB_PG_BIT 56
#define FEATURE_ECO_DEEPCSTATE_BIT 57
#define FEATURE_CC6_BIT 58
-#define NUM_FEATURES 59
+#define FEATURE_GFX_EDC_BIT 59
+#define NUM_FEATURES 60
typedef struct {
// MP1_EXT_SCRATCH0
uint32_t DpmHandlerID : 8;
uint32_t ActivityMonitorID : 8;
uint32_t DpmTimerID : 8;
- uint32_t spare0 : 8;
+ uint32_t DpmHubID : 4;
+ uint32_t DpmHubTask : 4;
// MP1_EXT_SCRATCH1
uint32_t GfxStatus : 2;
uint32_t GfxoffStatus : 8;
@@ -109,9 +111,10 @@ typedef struct {
uint32_t spare1 : 16;
// MP1_EXT_SCRATCH2
uint32_t P2JobHandler : 32;
- // MP1_EXT_SCRATCH3
-// uint32_t spare2 : 32;
+ // MP1_EXT_SCRATCH3: used for postcodes
+
// MP1_EXT_SCRATCH4:6 are used by Kernel
+ // MP1_EXT_SCRATCH7: used by HW
} FwStatus_t;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
index 1ada0eb64663..7e69b3bd311b 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
@@ -97,9 +97,16 @@
#define PPSMC_MSG_StopDramLogging 0x3F
#define PPSMC_MSG_SetSoftMinCclk 0x40
#define PPSMC_MSG_SetSoftMaxCclk 0x41
-#define PPSMC_Message_Count 0x42
+#define PPSMC_MSG_SetDfPstateActiveLevel 0x42
+#define PPSMC_MSG_SetDfPstateSoftMinLevel 0x43
+#define PPSMC_MSG_SetCclkPolicy 0x44
+#define PPSMC_MSG_DramLogSetDramAddrHigh 0x45
+#define PPSMC_MSG_DramLogSetDramBufferSize 0x46
+#define PPSMC_MSG_RequestActiveWgp 0x47
+#define PPSMC_MSG_QueryActiveWgp 0x48
+#define PPSMC_Message_Count 0x49
-//Argument for PPSMC_MSG_GpuChangeState
+//Argument for PPSMC_MSG_GfxDeviceDriverReset
enum {
MODE1_RESET = 1,
MODE2_RESET = 2