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| author | Tim Gore <tim.gore@intel.com> | 2016-04-22 10:46:01 +0200 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2016-04-25 11:06:56 +0200 |
| commit | 050fc4653c3634762dca4e5cfdeb43a31163f056 (patch) | |
| tree | a47f0e0577623067d9bbe3d1ce498a6cdc132177 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Update DRIVER_DATE to 20160425 (diff) | |
| download | linux-050fc4653c3634762dca4e5cfdeb43a31163f056.tar.xz linux-050fc4653c3634762dca4e5cfdeb43a31163f056.zip | |
drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
This patch applies a performance enhancement workaround
based on analysis of DX and OCL S-Curve workloads. We
increase the General Priority Credits for L3SQ from the
hardware default of 56 to the max value 62, and decrease
the High Priority credits from 8 to 2.
v2: Only apply to B0 onwards
v3: Move w/a to per engine init, ie bxt_init_workarounds
Signed-off-by: Tim Gore <tim.gore@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461314761-36854-1-git-send-email-tim.gore@intel.com
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 58ac6c7c690b..25e229b609a7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6090,6 +6090,7 @@ enum skl_disp_power_wells { #define GEN8_L3SQCREG1 _MMIO(0xB100) #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 +#define BXT_WA_L3SQCREG1_DEFAULT 0xF84000 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |