diff options
| author | Andrew Lutomirski <luto@mit.edu> | 2009-11-08 19:49:51 +0100 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-12-08 15:32:51 +0100 |
| commit | 7e8b60faea972604c315634cff62d44803731ea9 (patch) | |
| tree | a9c6fb0426fd6eac03e974b4c3242218d5996f80 /drivers/gpu/drm/i915/i915_suspend.c | |
| parent | drm/i915: Set the error code after failing to insert new offset into mm ht. (diff) | |
| download | linux-7e8b60faea972604c315634cff62d44803731ea9.tar.xz linux-7e8b60faea972604c315634cff62d44803731ea9.zip | |
drm/i915: restore render clock gating on resume
Rather than restoring just a few clock gating registers on resume,
just reinitialize the whole thing.
Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Fixed up for RC6 support landed since the patch was written]
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_suspend.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 402a7eb2922c..00f6d97c7cc5 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -722,10 +722,6 @@ int i915_save_state(struct drm_device *dev) dev_priv->saveIMR = I915_READ(IMR); } - /* Clock gating state */ - dev_priv->saveD_STATE = I915_READ(D_STATE); - dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */ - /* Cache mode state */ dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); @@ -800,8 +796,7 @@ int i915_restore_state(struct drm_device *dev) } /* Clock gating state */ - I915_WRITE (D_STATE, dev_priv->saveD_STATE); - I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); + intel_init_clock_gating(dev); /* Cache mode state */ I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); |