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authorBen Skeggs <bskeggs@redhat.com>2020-07-20 03:19:14 +0200
committerBen Skeggs <bskeggs@redhat.com>2020-07-24 10:51:04 +0200
commit60cdadace3208001b4e24a1a4b102f767d5df3c2 (patch)
tree89c4763e80e0a3287239462f54808f13247159e7 /drivers/gpu/drm/nouveau/nv84_fence.c
parentdrm/nouveau/svm: use NVIDIA's headers for migrate_clear() (diff)
downloadlinux-60cdadace3208001b4e24a1a4b102f767d5df3c2.tar.xz
linux-60cdadace3208001b4e24a1a4b102f767d5df3c2.zip
drm/nouveau/fence: use NVIDIA's headers for emit()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv84_fence.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv84_fence.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index bc09e64fe6b8..ec282f90d2ac 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -30,20 +30,26 @@
#include <nvif/push206e.h>
+#include <nvhw/class/cl826f.h>
+
static int
nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
struct nvif_push *push = chan->chan.push;
int ret = PUSH_WAIT(push, 8);
if (ret == 0) {
- PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
- PUSH_NVSQ(push, NV826F,
- NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
- NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
- NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
- NV84_SUBCHAN_SEMAPHORE_TRIGGER,
- NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG,
- NV84_SUBCHAN_UEVENT, 0x00000000);
+ PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
+
+ PUSH_MTHD(push, NV826F, SEMAPHOREA,
+ NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
+
+ SEMAPHOREB, lower_32_bits(virtual),
+ SEMAPHOREC, sequence,
+
+ SEMAPHORED,
+ NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),
+
+ NON_STALLED_INTERRUPT, 0);
PUSH_KICK(push);
}
return ret;