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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-10-28 15:56:23 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-11-01 20:25:49 +0100 |
| commit | d5693761b2b4ff530c8af8af9ec55b6eae76e617 (patch) | |
| tree | b13dca8d53f885279ffa3f0911948472b512cc23 /drivers/gpu/drm/radeon/sid.h | |
| parent | drm/radeon: fix endian handling in rlc buffer setup (diff) | |
| download | linux-d5693761b2b4ff530c8af8af9ec55b6eae76e617.tar.xz linux-d5693761b2b4ff530c8af8af9ec55b6eae76e617.zip | |
drm/radeon/si: fix define for MC_SEQ_TRAIN_WAKEUP_CNTL
Typo in the register offset.
Noticed-by: Sylvain BERTRAND <sylware@legeek.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/sid.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 307ffdfd644c..5691a7c30686 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -478,7 +478,7 @@ #define STATE3_MASK (0x1f << 15) #define STATE3_SHIFT 15 -#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 +#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 #define TRAIN_DONE_D0 (1 << 30) #define TRAIN_DONE_D1 (1 << 31) |