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author | Thierry Reding <treding@nvidia.com> | 2014-06-26 21:41:53 +0200 |
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committer | Thierry Reding <treding@nvidia.com> | 2014-11-13 16:14:48 +0100 |
commit | df06b759f2cf4690fa9991edb1504ba39932b2bb (patch) | |
tree | 0365d27fb82b94d4569c8b86dd775838bedc5ff1 /drivers/gpu/drm/tegra/gem.h | |
parent | drm/tegra: Fix error handling cleanup (diff) | |
download | linux-df06b759f2cf4690fa9991edb1504ba39932b2bb.tar.xz linux-df06b759f2cf4690fa9991edb1504ba39932b2bb.zip |
drm/tegra: Add IOMMU support
When an IOMMU device is available on the platform bus, allocate an IOMMU
domain and attach the display controllers to it. The display controllers
can then scan out non-contiguous buffers by mapping them through the
IOMMU.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/gem.h')
-rw-r--r-- | drivers/gpu/drm/tegra/gem.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/gem.h b/drivers/gpu/drm/tegra/gem.h index 6538b56780c2..3dd4165f812a 100644 --- a/drivers/gpu/drm/tegra/gem.h +++ b/drivers/gpu/drm/tegra/gem.h @@ -38,6 +38,12 @@ struct tegra_bo { dma_addr_t paddr; void *vaddr; + struct drm_mm_node *mm; + unsigned long num_pages; + struct page **pages; + /* size of IOMMU mapping */ + size_t size; + struct tegra_bo_tiling tiling; }; |