diff options
| author | Tanmay Jagdale <tanmay@marvell.com> | 2021-09-01 15:10:49 +0200 |
|---|---|---|
| committer | Mathieu Poirier <mathieu.poirier@linaro.org> | 2021-10-27 19:44:34 +0200 |
| commit | 4d5d88baa6c838bf92ed6a63c50dd3167c5a4956 (patch) | |
| tree | c17b75202049543d81790072af1a54a6367e98f1 /drivers/hwtracing/coresight/coresight-tmc-etr.c | |
| parent | dt-bindings: coresight: Add burst size for TMC (diff) | |
| download | linux-4d5d88baa6c838bf92ed6a63c50dd3167c5a4956.tar.xz linux-4d5d88baa6c838bf92ed6a63c50dd3167c5a4956.zip | |
coresight: tmc: Configure AXI write burst size
The current driver sets the write burst size initiated by TMC-ETR on
AXI bus to a fixed value of 16. Make this configurable by reading the
value specified in fwnode. If not specified, then default to 16.
Introduced a "max_burst_size" variable in tmc_drvdata structure to
facilitate this change.
Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20210901131049.1365367-3-tanmay@marvell.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tmc-etr.c')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tmc-etr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index acdb59e0e661..0ac2a611110b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -982,7 +982,8 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) axictl = readl_relaxed(drvdata->base + TMC_AXICTL); axictl &= ~TMC_AXICTL_CLEAR_MASK; - axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16); + axictl |= TMC_AXICTL_PROT_CTL_B1; + axictl |= TMC_AXICTL_WR_BURST(drvdata->max_burst_size); axictl |= TMC_AXICTL_AXCACHE_OS; if (tmc_etr_has_cap(drvdata, TMC_ETR_AXI_ARCACHE)) { |