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| author | Steve Wise <swise@opengridcomputing.com> | 2014-04-09 16:38:27 +0200 |
|---|---|---|
| committer | Roland Dreier <roland@purestorage.com> | 2014-04-11 20:36:08 +0200 |
| commit | a03d9f94cc54199bf681729b16ba649d7206369e (patch) | |
| tree | e2bebbff12cd98b99d2e8110cdd1a4b8af5afea9 /drivers/infiniband/hw/cxgb4/qp.c | |
| parent | RDMA/cxgb4: SQ flush fix (diff) | |
| download | linux-a03d9f94cc54199bf681729b16ba649d7206369e.tar.xz linux-a03d9f94cc54199bf681729b16ba649d7206369e.zip | |
RDMA/cxgb4: Max fastreg depth depends on DSGL support
The max depth of a fastreg mr depends on whether the device supports
DSGL or not. So compute it dynamically based on the device support
and the module use_dsgl option.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb4/qp.c')
| -rw-r--r-- | drivers/infiniband/hw/cxgb4/qp.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c index 9b4a8b88908e..2c037e1746d3 100644 --- a/drivers/infiniband/hw/cxgb4/qp.c +++ b/drivers/infiniband/hw/cxgb4/qp.c @@ -566,7 +566,8 @@ static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); int rem; - if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) + if (wr->wr.fast_reg.page_list_len > + t4_max_fr_depth(use_dsgl)) return -EINVAL; wqe->fr.qpbinde_to_dcacpu = 0; |