diff options
| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-07-20 12:51:31 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-07-20 13:09:21 +0200 |
| commit | b2d3e3354e2a0d0e912308618ea33d0337f405c3 (patch) | |
| tree | e0906b67599aaf9e75a87abf5b72289da19b4ee5 /drivers/irqchip/Kconfig | |
| parent | irqchip: Add Loongson Extended I/O interrupt controller support (diff) | |
| download | linux-b2d3e3354e2a0d0e912308618ea33d0337f405c3.tar.xz linux-b2d3e3354e2a0d0e912308618ea33d0337f405c3.zip | |
irqchip: Add LoongArch CPU interrupt controller support
LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
controller that described in Section 7.4 of "LoongArch Reference Manual,
Vol 1". For more information please refer Documentation/loongarch/irq-
chip-model.rst.
LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
(Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
bits, so we expose the fwnode_handle to map them, and get mapped irq
by irq_create_mapping when using them.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1658314292-35346-13-git-send-email-lvjianmin@loongson.cn
Diffstat (limited to 'drivers/irqchip/Kconfig')
| -rw-r--r-- | drivers/irqchip/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8f077d353e67..f53164ccdc9f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -546,6 +546,16 @@ config EXYNOS_IRQ_COMBINER Say yes here to add support for the IRQ combiner devices embedded in Samsung Exynos chips. +config IRQ_LOONGARCH_CPU + bool + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + select GENERIC_IRQ_EFFECTIVE_AFF_MASK + help + Support for the LoongArch CPU Interrupt Controller. For details of + irq chip hierarchy on LoongArch platforms please read the document + Documentation/loongarch/irq-chip-model.rst. + config LOONGSON_LIOINTC bool "Loongson Local I/O Interrupt Controller" depends on MACH_LOONGSON64 |