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| author | Takahiro Kuwano <Takahiro.Kuwano@infineon.com> | 2023-07-26 09:52:52 +0200 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@linaro.org> | 2023-07-26 11:39:11 +0200 |
| commit | 7d896a94bf74ba0cf3a9d16d9cef98062e2017d2 (patch) | |
| tree | ed6bb998a4c47ab0ef0a6334255d7fc83d12375d /drivers/mtd | |
| parent | mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset (diff) | |
| download | linux-7d896a94bf74ba0cf3a9d16d9cef98062e2017d2.tar.xz linux-7d896a94bf74ba0cf3a9d16d9cef98062e2017d2.zip | |
mtd: spi-nor: spansion: add MCP support in set_octal_dtr()
Infineon multi-chip package (MCP) devices require the Octal DTR
configuraion to be set on each die. We can access to configuration
registers in each die by using params->n_dice and params->vreg_offset[]
populated from SFDP. Add MCP support in set_octal_dtr().
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Link: https://lore.kernel.org/r/20230726075257.12985-7-tudor.ambarus@linaro.org
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/spansion.c | 33 |
1 files changed, 19 insertions, 14 deletions
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6d8dd800ba65..b3a710985f84 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -204,17 +204,19 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) const struct spi_nor_flash_parameter *params = nor->params; u8 *buf = nor->bouncebuf; u64 addr; - int ret; + int i, ret; - addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; - ret = cypress_nor_set_memlat(nor, addr); - if (ret) - return ret; + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; + ret = cypress_nor_set_memlat(nor, addr); + if (ret) + return ret; - addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret = cypress_nor_set_octal_dtr_bits(nor, addr); - if (ret) - return ret; + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_set_octal_dtr_bits(nor, addr); + if (ret) + return ret; + } /* Read flash ID to make sure the switch was successful. */ ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, @@ -249,14 +251,17 @@ static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params = nor->params; u8 *buf = nor->bouncebuf; u64 addr; - int ret; + int i, ret; - addr = nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret = cypress_nor_set_single_spi_bits(nor, addr); - if (ret) - return ret; + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_set_single_spi_bits(nor, addr); + if (ret) + return ret; + } /* Read flash ID to make sure the switch was successful. */ ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); |