diff options
| author | Maxime Chevallier <maxime.chevallier@bootlin.com> | 2019-03-27 09:44:15 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-03-27 19:10:58 +0100 |
| commit | 147c538e7975ce9c6c4fdd175fd703aec4280ec8 (patch) | |
| tree | 1fb7ea5feeb3b75e849cc94c5aa31bd5ffa5fbf4 /drivers/net/ethernet/marvell | |
| parent | net: mvpp2: cls: Use iterators to go through the cls_table (diff) | |
| download | linux-147c538e7975ce9c6c4fdd175fd703aec4280ec8.tar.xz linux-147c538e7975ce9c6c4fdd175fd703aec4280ec8.zip | |
net: mvpp2: cls: Write C2 TCAM data last when writing a C2 entry
When writing a C2 entry to hardware, some registers writes will only
take effect when the TCAM_DATA4 register is written. This includes all
C2 TCAM registers, and the C2 invalidate register.
To make sure we always write C2 entries correctly, document that
behaviour with a comment, and move TCAM writes to the end of the
mvpp2_cls_c2_write helper.
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell')
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c index 96358efcc018..335714e1bbea 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c @@ -748,19 +748,19 @@ static void mvpp2_cls_c2_write(struct mvpp2 *priv, { mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2->index); - /* Write TCAM */ - mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]); - mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]); - mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]); - mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]); - mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]); - mvpp2_write(priv, MVPP22_CLS_C2_ACT, c2->act); mvpp2_write(priv, MVPP22_CLS_C2_ATTR0, c2->attr[0]); mvpp2_write(priv, MVPP22_CLS_C2_ATTR1, c2->attr[1]); mvpp2_write(priv, MVPP22_CLS_C2_ATTR2, c2->attr[2]); mvpp2_write(priv, MVPP22_CLS_C2_ATTR3, c2->attr[3]); + + mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]); + mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]); + mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]); + mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]); + /* Writing TCAM_DATA4 flushes writes to TCAM_DATA0-4 and INV to HW */ + mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]); } void mvpp2_cls_c2_read(struct mvpp2 *priv, int index, |