diff options
| author | Omkar Kulkarni <okulkarni@marvell.com> | 2021-10-04 08:58:46 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-10-04 13:55:49 +0200 |
| commit | b90cb5385af78d5bc9f439c0d0d7e188202c39b9 (patch) | |
| tree | dc48c4f8fa72554ceacc2d1dd7b5e35a8e199adf /drivers/net/ethernet/qlogic/qed/qed_reg_addr.h | |
| parent | qed: Use enum as per FW 8.59.1.0 in qed_iro_hsi.h (diff) | |
| download | linux-b90cb5385af78d5bc9f439c0d0d7e188202c39b9.tar.xz linux-b90cb5385af78d5bc9f439c0d0d7e188202c39b9.zip | |
qed: Update FW init functions to support FW 8.59.1.0
The qed_init_fw_func.c and qed_init_ops.c updated to support FW
version 8.59.1.0.
- Support 16-bit VPORT WFQ (weighted fair queueing) weights.
- Support WFQ (weighted fair queueing) weight per VPORT + TC.
- Support allocation of Tx PQs(physical queues) per PF,VF.
- Modify Global RL (rate limiter) upper bound configuration.
- Update FW operation functions.
- Update iro_arr[] array.
This patch also fixes the existing checkpatch warnings and few important
checks.
Signed-off-by: Ariel Elior <aelior@marvell.com>
Signed-off-by: Shai Malin <smalin@marvell.com>
Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com>
Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_reg_addr.h')
| -rw-r--r-- | drivers/net/ethernet/qlogic/qed/qed_reg_addr.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h index fd338a8dbedc..7f668ecd73fe 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h +++ b/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h @@ -126,6 +126,8 @@ 0x1009c4UL #define QM_REG_PF_EN \ 0x2f2ea4UL +#define QM_REG_RLGLBLUPPERBOUND \ + 0x2f3c00UL #define TCFC_REG_WEAK_ENABLE_VF \ 0x2d0704UL #define TCFC_REG_STRONG_ENABLE_PF \ @@ -576,7 +578,7 @@ #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL #define PRS_REG_GRE_PROTOCOL 0x1f0734UL #define PRS_REG_VXLAN_PORT 0x1f0738UL -#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL +#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) @@ -595,8 +597,9 @@ #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL -#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL -#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL +#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL +#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL + #define NIG_REG_NGE_IP_ENABLE 0x508b28UL #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL @@ -606,7 +609,10 @@ #define QM_REG_WFQPFWEIGHT 0x2f4e80UL #define QM_REG_WFQVPWEIGHT 0x2fa000UL - +#define QM_REG_WFQVPUPPERBOUND \ + 0x2fb000UL +#define QM_REG_WFQVPCRD \ + 0x2fc000UL #define PGLCS_REG_DBG_SELECT_K2_E5 \ 0x001d14UL #define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \ |