diff options
| author | Jim Quinlan <james.quinlan@broadcom.com> | 2024-08-16 00:57:18 +0200 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-09-04 15:58:29 +0200 |
| commit | 46cb27f671f2148005ee556b895d6372c6608e27 (patch) | |
| tree | c504d15d6791bbc4c3e4f920533f05c872778e0d /drivers/pci/controller/pcie-brcmstb.c | |
| parent | PCI: brcmstb: Use common error handling code in brcm_pcie_probe() (diff) | |
| download | linux-46cb27f671f2148005ee556b895d6372c6608e27.tar.xz linux-46cb27f671f2148005ee556b895d6372c6608e27.zip | |
PCI: brcmstb: Use bridge reset if available
The 7712 SoC has a bridge reset which can be described in the device
tree.
Use it if present. Otherwise, continue to use the legacy method to
reset the bridge.
Link: https://lore.kernel.org/linux-pci/20240815225731.40276-6-james.quinlan@broadcom.com
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
[kwilczynski: commit log, refactored function brcm_pcie_bridge_sw_init_set_generic()]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Diffstat (limited to 'drivers/pci/controller/pcie-brcmstb.c')
| -rw-r--r-- | drivers/pci/controller/pcie-brcmstb.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 790a149f6581..f8b6765d2e65 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -265,6 +265,7 @@ struct brcm_pcie { enum pcie_type type; struct reset_control *rescal; struct reset_control *perst_reset; + struct reset_control *bridge_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -732,9 +733,18 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus, static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) { - u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; + u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; + if (pcie->bridge_reset) { + if (val) + reset_control_assert(pcie->bridge_reset); + else + reset_control_deassert(pcie->bridge_reset); + + return; + } + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); tmp = (tmp & ~mask) | ((val << shift) & mask); writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); @@ -1621,10 +1631,16 @@ static int brcm_pcie_probe(struct platform_device *pdev) if (IS_ERR(pcie->perst_reset)) return PTR_ERR(pcie->perst_reset); + pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); + if (IS_ERR(pcie->bridge_reset)) + return PTR_ERR(pcie->bridge_reset); + ret = clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); + pcie->bridge_sw_init_set(pcie, 0); + ret = reset_control_reset(pcie->rescal); if (ret) { clk_disable_unprepare(pcie->clk); |