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authorSajid Dalvi <sdalvi@google.com>2022-09-21 23:27:35 +0200
committerBjorn Helgaas <bhelgaas@google.com>2022-09-29 21:31:40 +0200
commit3e347969a5776947a115649dae740a9ed47473f5 (patch)
treebbc9ff6cdf06d8441d93ffc8f225cf082ba56fb5 /drivers/pci/pci.c
parentPCI/PM: Simplify pci_pm_suspend_noirq() (diff)
downloadlinux-3e347969a5776947a115649dae740a9ed47473f5.tar.xz
linux-3e347969a5776947a115649dae740a9ed47473f5.zip
PCI/PM: Reduce D3hot delay with usleep_range()
PCIe r6.0, sec 5.9, requires a 10ms delay between programming a device to change to or from D3hot and the time the device is next accessed (unless Readiness Notifications are used). The 10ms value (PCI_PM_D3HOT_WAIT) doesn't appear directly here because some chipsets require 120ms for devices *below* them (pci_pm_d3hot_delay) and some devices require more or less than 10ms (dev->d3hot_delay). But msleep(10) typically waits about *20*ms, which is more than we need. Switch to usleep_range() to improve the delay accuracy. Based on a commit from Sajid in the Pixel 6 kernel tree [1]. On a Pixel 6, the 10ms delay for the Exynos PCIe device delayed for an average of 19ms. Switching to usleep_range() decreased the resume time by about 9ms. [1] https://android.googlesource.com/kernel/gs/+/18a8cad68d8e6d50f339a716a18295e6d987cee3 [bhelgaas commit log, add timers-howto.rst link] Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/timers/timers-howto.rst?id=v5.19#n73 Link: https://lore.kernel.org/r/20220921212735.2131588-1-willmcvicker@google.com Signed-off-by: Sajid Dalvi <sdalvi@google.com> Signed-off-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Diffstat (limited to 'drivers/pci/pci.c')
-rw-r--r--drivers/pci/pci.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 107afa0a5b03..92c6f7e5ca2e 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -66,13 +66,15 @@ struct pci_pme_device {
static void pci_dev_d3_sleep(struct pci_dev *dev)
{
- unsigned int delay = dev->d3hot_delay;
-
- if (delay < pci_pm_d3hot_delay)
- delay = pci_pm_d3hot_delay;
-
- if (delay)
- msleep(delay);
+ unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
+ unsigned int upper;
+
+ if (delay_ms) {
+ /* Use a 20% upper bound, 1ms minimum */
+ upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
+ usleep_range(delay_ms * USEC_PER_MSEC,
+ (delay_ms + upper) * USEC_PER_MSEC);
+ }
}
bool pci_reset_supported(struct pci_dev *dev)