diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2015-08-11 05:07:06 +0200 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2015-08-11 05:07:06 +0200 |
| commit | 92b19ff50e8f242392d78b2aacc5b5b672f1796b (patch) | |
| tree | 463927d91228174419ba1fe327f3cec6b9a2615a /drivers/pci/probe.c | |
| parent | arch, drivers: don't include <asm/io.h> directly, use <linux/io.h> instead (diff) | |
| download | linux-92b19ff50e8f242392d78b2aacc5b5b672f1796b.tar.xz linux-92b19ff50e8f242392d78b2aacc5b5b672f1796b.zip | |
cleanup IORESOURCE_CACHEABLE vs ioremap()
Quoting Arnd:
I was thinking the opposite approach and basically removing all uses
of IORESOURCE_CACHEABLE from the kernel. There are only a handful of
them.and we can probably replace them all with hardcoded
ioremap_cached() calls in the cases they are actually useful.
All existing usages of IORESOURCE_CACHEABLE call ioremap() instead of
ioremap_nocache() if the resource is cacheable, however ioremap() is
uncached by default. Clearly none of the existing usages care about the
cacheability. Particularly devm_ioremap_resource() never worked as
advertised since it always fell back to plain ioremap().
Clean this up as the new direction we want is to convert
ioremap_<type>() usages to memremap(..., flags).
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/pci/probe.c')
| -rw-r--r-- | drivers/pci/probe.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index cefd636681b6..8ed37dd04056 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -326,8 +326,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; dev->rom_base_reg = rom; res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | - IORESOURCE_READONLY | IORESOURCE_CACHEABLE | - IORESOURCE_SIZEALIGN; + IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; __pci_read_base(dev, pci_bar_mem32, res, rom); } } |