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| author | Lucas Stach <l.stach@pengutronix.de> | 2017-02-02 18:15:31 +0100 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-02-08 20:33:57 +0100 |
| commit | 8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256 (patch) | |
| tree | c764dfcd5a0d894c3f3a9ecf625156c634aa6d3a /drivers/pci | |
| parent | PCI: mvebu: Handle changes to the bridge windows while enabled (diff) | |
| download | linux-8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256.tar.xz linux-8ed81ec82a8c57c3a6ad69b4c4d3e4801163c256.zip | |
PCI: mvebu: Change delay after reset to the PCIe spec mandated 100ms
The current default of 20ms cause some devices, which are slow to
initialize, to not show up during the bus scanning. Change this to the
PCIe spec mandated 100ms and document this in the DT binding.
From PCIe base spec rev 3.0, chapter "6.6.1. Conventional Reset":
To allow components to perform internal initialization, system software
must wait a specified minimum period following the end of a Conventional
Reset of one or more devices before it is permitted to issue
Configuration Requests to those devices.
With a Downstream Port that does not support Link speeds greater than 5.0
GT/s, software must wait a minimum of 100 ms before sending a
Configuration Request to the device immediately below that Port.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-mvebu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c index 90e0b6f134ad..cd7d51988738 100644 --- a/drivers/pci/host/pci-mvebu.c +++ b/drivers/pci/host/pci-mvebu.c @@ -1181,7 +1181,7 @@ static int mvebu_pcie_powerup(struct mvebu_pcie_port *port) return ret; if (port->reset_gpio) { - u32 reset_udelay = 20000; + u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; of_property_read_u32(port->dn, "reset-delay-us", &reset_udelay); |