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| author | Hojin Nam <hj96.nam@samsung.com> | 2024-02-16 02:45:22 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2024-02-20 13:04:07 +0100 |
| commit | 802379b8f9e169293e9ba7089e5f1a6340e2e7a3 (patch) | |
| tree | d68494809a2b34a9548ba7c1a4b79d162280b64f /drivers/perf/cxl_pmu.c | |
| parent | arm64/sve: Lower the maximum allocation for the SVE ptrace regset (diff) | |
| download | linux-802379b8f9e169293e9ba7089e5f1a6340e2e7a3.tar.xz linux-802379b8f9e169293e9ba7089e5f1a6340e2e7a3.zip | |
perf: CXL: fix CPMU filter value mask length
CPMU filter value is described as 4B length in CXL r3.0 8.2.7.2.2.
However, it is used as 2B length in code and comments.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Hojin Nam <hj96.nam@samsung.com>
Link: https://lore.kernel.org/r/20240216014522.32321-1-hj96.nam@samsung.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf/cxl_pmu.c')
| -rw-r--r-- | drivers/perf/cxl_pmu.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c index bc0d414a6aff..308c9969642e 100644 --- a/drivers/perf/cxl_pmu.c +++ b/drivers/perf/cxl_pmu.c @@ -59,7 +59,7 @@ #define CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK GENMASK_ULL(63, 59) #define CXL_PMU_FILTER_CFG_REG(n, f) (0x400 + 4 * ((f) + (n) * 8)) -#define CXL_PMU_FILTER_CFG_VALUE_MSK GENMASK(15, 0) +#define CXL_PMU_FILTER_CFG_VALUE_MSK GENMASK(31, 0) #define CXL_PMU_COUNTER_REG(n) (0xc00 + 8 * (n)) @@ -314,9 +314,9 @@ static bool cxl_pmu_config1_get_edge(struct perf_event *event) } /* - * CPMU specification allows for 8 filters, each with a 16 bit value... - * So we need to find 8x16bits to store it in. - * As the value used for disable is 0xffff, a separate enable switch + * CPMU specification allows for 8 filters, each with a 32 bit value... + * So we need to find 8x32bits to store it in. + * As the value used for disable is 0xffff_ffff, a separate enable switch * is needed. */ @@ -642,7 +642,7 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags) if (cxl_pmu_config1_hdm_filter_en(event)) cfg = cxl_pmu_config2_get_hdm_decoder(event); else - cfg = GENMASK(15, 0); /* No filtering if 0xFFFF_FFFF */ + cfg = GENMASK(31, 0); /* No filtering if 0xFFFF_FFFF */ writeq(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0)); } |