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authorRahul Rameshbabu <rrameshbabu@nvidia.com>2023-06-12 23:14:56 +0200
committerDavid S. Miller <davem@davemloft.net>2023-06-20 10:02:33 +0200
commitc3b60ab7a4dff6e6e608e685b70ddc3d6b2aca81 (patch)
tree5ca798c8795ce133b62d61fc7400919ad9f52dd2 /drivers/ptp/ptp_clock.c
parenttestptp: Add support for testing ptp_clock_info .adjphase callback (diff)
downloadlinux-c3b60ab7a4dff6e6e608e685b70ddc3d6b2aca81.tar.xz
linux-c3b60ab7a4dff6e6e608e685b70ddc3d6b2aca81.zip
ptp: Add .getmaxphase callback to ptp_clock_info
Enables advertisement of the maximum offset supported by the phase control functionality of PHCs. The callback is used to return an error if an offset not supported by the PHC is used in ADJ_OFFSET. The ioctls PTP_CLOCK_GETCAPS and PTP_CLOCK_GETCAPS2 now advertise the maximum offset a PHC's phase control functionality is capable of supporting. Introduce new sysfs node, max_phase_adjustment. Cc: Jakub Kicinski <kuba@kernel.org> Cc: Shuah Khan <shuah@kernel.org> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Maciek Machnikowski <maciek@machnikowski.net> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ptp/ptp_clock.c')
-rw-r--r--drivers/ptp/ptp_clock.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
index 790f9250b381..80f74e38c2da 100644
--- a/drivers/ptp/ptp_clock.c
+++ b/drivers/ptp/ptp_clock.c
@@ -135,11 +135,15 @@ static int ptp_clock_adjtime(struct posix_clock *pc, struct __kernel_timex *tx)
ptp->dialed_frequency = tx->freq;
} else if (tx->modes & ADJ_OFFSET) {
if (ops->adjphase) {
+ s32 max_phase_adj = ops->getmaxphase(ops);
s32 offset = tx->offset;
if (!(tx->modes & ADJ_NANO))
offset *= NSEC_PER_USEC;
+ if (offset > max_phase_adj || offset < -max_phase_adj)
+ return -ERANGE;
+
err = ops->adjphase(ops, offset);
}
} else if (tx->modes == 0) {