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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2014-09-25 12:06:45 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-09-28 23:22:09 +0200 |
| commit | b1a6d3ecf806457d3e76ac0044db424be3c9422d (patch) | |
| tree | d0951a96258a0fd38b88f01bf56cbbb525fb0f4f /drivers/reset | |
| parent | defxx: Correct DEFEA's ESIC port I/O accesses (diff) | |
| download | linux-b1a6d3ecf806457d3e76ac0044db424be3c9422d.tar.xz linux-b1a6d3ecf806457d3e76ac0044db424be3c9422d.zip | |
defxx: DEFEA's Burst Holdoff register initialization fix
Use the mask rather than bit number macro to initialize the chip select
control bit for PDQ register space decoding in the Burst Holdoff register.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/reset')
0 files changed, 0 insertions, 0 deletions