diff options
| author | Shreyas Joshi <shreyas.joshi@biamp.com> | 2020-07-10 23:16:55 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-07-22 02:55:51 +0200 |
| commit | ce8e60fe4f517b3b2b1deb44cf364a9080521567 (patch) | |
| tree | e98b9f577a2842064a452c52062f85a15d89bcfb /drivers/spi | |
| parent | spi: lpspi: fix the imbalance of runtime pm function call (diff) | |
| download | linux-ce8e60fe4f517b3b2b1deb44cf364a9080521567.tar.xz linux-ce8e60fe4f517b3b2b1deb44cf364a9080521567.zip | |
spi: spi-cadence: add support for chip select high
The spi cadence driver should support spi-cs-high in mode bits
so that the peripherals that needs the chip select to be high active can
use it. Add the SPI-CS-HIGH flag in the supported mode bits.
Signed-off-by: Shreyas Joshi <shreyas.joshi@biamp.com>
Link: https://lore.kernel.org/r/20200710211655.1564-1-shreyas.joshi@biamp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-cadence.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 82a0ee09cbe1..2b6b9c1ad9d0 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -556,7 +556,7 @@ static int cdns_spi_probe(struct platform_device *pdev) master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; master->set_cs = cdns_spi_chipselect; master->auto_runtime_pm = true; - master->mode_bits = SPI_CPOL | SPI_CPHA; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; /* Set to default valid value */ master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4; |