diff options
| author | Andrew Jones <ajones@ventanamicro.com> | 2024-09-09 10:56:11 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-10-02 15:12:18 +0200 |
| commit | 4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa (patch) | |
| tree | 8cc06fdab94ab8a7c5acbaae66b18cce55555ed9 /drivers | |
| parent | irqchip/ocelot: Comment sticky register clearing code (diff) | |
| download | linux-4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa.tar.xz linux-4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa.zip | |
irqchip/riscv-imsic: Fix output text of base address
The "per-CPU IDs ... at base ..." info log is outputting a physical
address, not a PPN.
Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/all/20240909085610.46625-2-ajones@ventanamicro.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/irqchip/irq-riscv-imsic-platform.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 64905e6f52d7..c708780e8760 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -341,7 +341,7 @@ int imsic_irqdomain_init(void) imsic->fwnode, global->hart_index_bits, global->guest_index_bits); pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", imsic->fwnode, global->group_index_bits, global->group_index_shift); - pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n", + pr_info("%pfwP: per-CPU IDs %d at base address %pa\n", imsic->fwnode, global->nr_ids, &global->base_addr); pr_info("%pfwP: total %d interrupts available\n", imsic->fwnode, num_possible_cpus() * (global->nr_ids - 1)); |