diff options
| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2022-04-24 08:36:37 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-03-31 17:18:42 +0200 |
| commit | 52b36510a175607b653e6ab0fffaca64ab8903e2 (patch) | |
| tree | f79725acb2ea916a46ef926d31d5341a4c25a641 /drivers | |
| parent | drm/radeon: Only build fbdev if DRM_FBDEV_EMULATION is set (diff) | |
| download | linux-52b36510a175607b653e6ab0fffaca64ab8903e2.tar.xz linux-52b36510a175607b653e6ab0fffaca64ab8903e2.zip | |
drm/amdgpu: add nbio v7_9_0 ip headers
Add nbio v7_9_0 register offset and shift masks
header files
v2: update headers (Alex)
v3: squash in updates (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h | 10002 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h | 38900 |
2 files changed, 48902 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h new file mode 100644 index 000000000000..033f2796c1e3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h @@ -0,0 +1,10002 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_7_9_0_OFFSET_HEADER +#define _nbio_7_9_0_OFFSET_HEADER + + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define regBIF_BX0_PCIE_INDEX 0x000c +#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA 0x000d +#define regBIF_BX0_PCIE_DATA_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2 0x000e +#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA2 0x000f +#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX_HI 0x0010 +#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2_HI 0x0011 +#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 +#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 +#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 +#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 +#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 +#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_0 0x0038 +#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_1 0x0039 +#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_2 0x003a +#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_4 0x003c +#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_5 0x003d +#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_7 0x003f +#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_8 0x0040 +#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_9 0x0041 +#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_10 0x0042 +#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_11 0x0043 +#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_12 0x0044 +#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_13 0x0045 +#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_14 0x0046 +#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_15 0x0047 +#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c +#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d +#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e +#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 +#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 +#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 +#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 +#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 +#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 +#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 +#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 +#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 +#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 +#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a +#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b +#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c +#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d +#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e +#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f +#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_0 0x0090 +#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_1 0x0091 +#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_2 0x0092 +#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_3 0x0093 +#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_4 0x0094 +#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_5 0x0095 +#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_6 0x0096 +#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_7 0x0097 +#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_8 0x0098 +#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_9 0x0099 +#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_10 0x009a +#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_11 0x009b +#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_12 0x009c +#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_13 0x009d +#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_14 0x009e +#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_15 0x009f +#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 +#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 +#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 +#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 +#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 +#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 +#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 +#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 +#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 +#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 +#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa +#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab +#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_PF0_MM_INDEX 0x0000 +#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_PF0_MM_DATA 0x0001 +#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_PF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 +#define regBIF_BX_PF0_RSMU_INDEX 0x0000 +#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_DATA 0x0001 +#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 +#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 +#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BUS_CNTL 0x00e7 +#define regBIF_BX0_BUS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH0 0x00e8 +#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH1 0x00e9 +#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_EN 0x00ed +#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 +#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee +#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_CNTL 0x00f0 +#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL 0x00f1 +#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 +#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 +#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 +#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd +#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN 0x0100 +#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BACO_CNTL 0x010b +#define regBIF_BX0_BACO_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c +#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define regBIF_BX0_MEM_TYPE_CNTL 0x0111 +#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_CNTL 0x012f +#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_BASE 0x0130 +#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_RPTR 0x0131 +#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR 0x0132 +#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define regBIF_BX0_MAILBOX_INDEX 0x0135 +#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 +#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 +#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0146 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0147 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0148 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0149 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x014a +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_RESET_EN 0x0088 +#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c +#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 +#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 +#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca +#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 +#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 +#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 +#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 +#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 +#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 +#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 +#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0024 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0025 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0026 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0032 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0033 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0034 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0035 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0036 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0037 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0038 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0039 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x003a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003b +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003c +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003d +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x3480 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +// base address: 0x0 +#define regGDC0_A2S_CNTL_CL0 0x0000 +#define regGDC0_A2S_CNTL_CL0_BASE_IDX 3 +#define regGDC0_A2S_CNTL_CL1 0x0001 +#define regGDC0_A2S_CNTL_CL1_BASE_IDX 3 +#define regGDC0_A2S_CNTL3_CL0 0x0018 +#define regGDC0_A2S_CNTL3_CL0_BASE_IDX 3 +#define regGDC0_A2S_CNTL3_CL1 0x0019 +#define regGDC0_A2S_CNTL3_CL1_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW0 0x0030 +#define regGDC0_A2S_CNTL_SW0_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW1 0x0031 +#define regGDC0_A2S_CNTL_SW1_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW2 0x0032 +#define regGDC0_A2S_CNTL_SW2_BASE_IDX 3 +#define regGDC0_A2S_TAG_ALLOC_0 0x003d +#define regGDC0_A2S_TAG_ALLOC_0_BASE_IDX 3 +#define regGDC0_A2S_TAG_ALLOC_1 0x003e +#define regGDC0_A2S_TAG_ALLOC_1_BASE_IDX 3 +#define regGDC0_A2S_MISC_CNTL 0x0041 +#define regGDC0_A2S_MISC_CNTL_BASE_IDX 3 +#define regGDC0_SHUB_REGS_IF_CTL 0x0043 +#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 3 +#define regGDC0_NGDC_MGCG_CTRL 0x004a +#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_RESERVED_0 0x004b +#define regGDC0_NGDC_RESERVED_0_BASE_IDX 3 +#define regGDC0_NGDC_RESERVED_1 0x004c +#define regGDC0_NGDC_RESERVED_1_BASE_IDX 3 +#define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x004f +#define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 +#define regGDC0_ATDMA_MISC_CNTL 0x005d +#define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 3 +#define regGDC0_S2A_MISC_CNTL 0x005f +#define regGDC0_S2A_MISC_CNTL_BASE_IDX 3 +#define regGDC0_NGDC_PG_MISC_CTRL 0x0078 +#define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_PGMST_CTRL 0x0079 +#define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_PGSLV_CTRL 0x007a +#define regGDC0_NGDC_PGSLV_CTRL_BASE_IDX 3 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgPCIE_SRIOV_CAP 0x0334 +#define cfgPCIE_SRIOV_CONTROL 0x0338 +#define cfgPCIE_SRIOV_STATUS 0x033a +#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgPCIE_SRIOV_NUM_VFS 0x0340 +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x050c +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0700 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0704 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0708 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x070c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0710 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0714 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0718 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x071c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0720 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0724 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0728 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0730 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0734 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0738 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x073c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0740 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0744 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0748 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x074c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0750 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0754 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0758 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x075c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0760 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0764 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0768 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x076c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0770 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0774 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0778 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x077c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0780 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0784 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0788 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x078c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0790 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0794 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0798 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x079c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x07a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x07a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x07a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x07ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x07b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x07c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x07c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x07c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x07cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x07d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x07f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x07f4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x07f8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x07fc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x0800 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x0804 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x0808 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x080c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x0810 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0820 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0824 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0828 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x082c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0830 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0834 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0838 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x083c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0840 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x0850 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x0854 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x0858 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x085c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x0860 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x0864 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x0868 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x086c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x0870 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x0880 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x0884 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x0888 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x088c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x0890 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x0894 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x0898 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x089c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x08a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x08b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x08b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x08b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x08bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x08c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x08c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x08c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x08cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x08d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x08e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x08e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x08e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x08ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x08f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x08f4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x08f8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x08fc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x0900 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x0910 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x0914 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x0918 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x091c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x0920 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x0924 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x0928 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x092c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x0930 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x0940 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x0944 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x0948 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x094c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x0950 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x0954 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x0958 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x095c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x0960 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x0970 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x0974 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x0978 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x097c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x0980 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x0984 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x0988 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x098c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x0990 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x09a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x09a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x09a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x09ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x09b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x09b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x09b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x09bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x09c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x09d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x09d4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x09d8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x09dc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x09e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x09e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x09e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x09ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x09f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x0a00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x0a04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x0a08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x0a0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x0a10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x0a14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x0a18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x0a1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x0a20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x0a30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x0a34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x0a38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x0a3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x0a40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x0a44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x0a48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x0a4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x0a50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x0a60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x0a64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x0a68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x0a6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x0a70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x0a74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x0a78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x0a7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x0a80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x0a90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x0a94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x0a98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x0a9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x0aa0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x0aa4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x0aa8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x0aac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x0ab0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x0ac0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x0ac4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x0ac8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x0acc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x0ad0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x0ad4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x0ad8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x0adc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x0ae0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x0af0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x0af4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x0af8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x0afc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x0b00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x0b04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x0b08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x0b0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x0b10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x0b20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x0b24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x0b28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x0b2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x0b30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x0b34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x0b38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x0b3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x0b40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x0b50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x0b54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x0b58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x0b5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x0b60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x0b64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x0b68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x0b6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x0b70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x0b80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x0b84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x0b88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x0b8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x0b90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x0b94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x0b98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x0b9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x0ba0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x0c00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x0c04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x0c08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x0c0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x0c10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x0c14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x0c18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x0c1c + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x10100000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 +#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_STATUS 0x0001 +#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 +#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 +#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_HEADER 0x0003 +#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BIST 0x0003 +#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d +#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b +#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0044 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0045 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0046 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0051 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0052 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0055 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0056 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0057 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0058 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0059 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x005a +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x005b +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x005c +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x005d +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x005e +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x005f +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0060 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0061 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0062 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0063 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0064 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0065 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x009c +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x009d +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x009e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x00a6 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x00a6 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x00a8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x00a9 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x00a9 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x0100 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x0101 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x0102 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x0105 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0106 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0107 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0108 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0109 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x010a +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0114 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0115 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0115 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0116 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0116 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0117 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0117 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0118 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0118 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0119 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0119 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x011a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x011a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x011b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x011b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x011c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x011c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x011d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x011d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x011e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x011e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x011f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x011f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x0120 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x0120 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x0121 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x0121 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x0122 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x0122 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x0123 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x0123 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x0124 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x0124 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x0125 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x0125 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x0141 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0142 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0143 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10044 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10045 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10046 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10055 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10056 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10057 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10058 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10059 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1005a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x1005b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x1005c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1005d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1005e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x10062 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10063 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10064 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10065 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x10080 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x10081 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x10082 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x10083 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x10084 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x10085 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x1008a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x1008b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x1008c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x10092 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x10093 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x10094 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x100a8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x100a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x100a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x100ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x100ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x100ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x100b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x100b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x100b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x100b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x100b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x100b4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x100b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x100b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x100bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x100bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x100bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x100be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x100bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x100c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x100c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x100c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x100c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x100c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x100c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x100ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x100cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x100cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x100cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x100ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x100ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x100d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x100d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x10101 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x10102 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x10105 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10106 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10107 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10115 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10115 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10116 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10116 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10117 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10117 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10118 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10118 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10119 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10119 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1011a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1011a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1011b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1011b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1011c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1011c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1011d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1011d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1011e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1011e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1011f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1011f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x10120 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x10120 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x10121 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x10121 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x10122 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x10122 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x10123 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x10123 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x10124 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x10124 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x10125 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x10125 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x10141 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10142 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10143 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x101c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x101c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x101c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x101c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x101c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x101c6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x101c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x101c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x101c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x101ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x101cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x101cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x101ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x101cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x101d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x101d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x101d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x101d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x101d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x101d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x101d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x101da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x101db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x101dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x101de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x101df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x101e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x101e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x101e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x101e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x101e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x101e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x101e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x101e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x101e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x101e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x101ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x101eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x101f0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x101f1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x101f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x101f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x101fc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x101fd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x101fe +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x101ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x10200 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x10201 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x10202 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x10203 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x10204 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x10208 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x10209 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x1020a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x1020b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x1020c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x1020d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x1020e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x1020f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x10210 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x10214 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x10215 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x10216 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x10217 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x10218 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x10219 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x1021a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x1021b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x1021c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x10220 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x10221 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x10222 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x10223 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x10224 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x10225 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x10226 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x10227 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x10228 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x1022c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x1022d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x1022e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x1022f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x10230 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x10231 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x10232 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x10233 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x10234 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x10238 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x10239 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x1023a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x1023b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x1023c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x1023d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x1023e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x1023f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x10240 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x10244 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x10245 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x10246 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x10247 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x10248 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x10249 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x1024a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x1024b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x1024c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x10250 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x10251 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x10252 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x10253 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x10254 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x10255 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x10256 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x10257 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x10258 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x1025c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x1025d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x1025e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x1025f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x10260 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x10261 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x10262 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x10263 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x10264 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x10268 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x10269 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x1026a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x1026b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x1026c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x1026d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x1026e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x1026f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x10270 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x10274 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x10275 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x10276 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x10277 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x10278 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x10279 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x1027a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x1027b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x1027c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x10280 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x10281 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x10282 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x10283 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x10284 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x10285 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x10286 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x10287 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x10288 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x1028c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x1028d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x1028e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x1028f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x10290 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x10291 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x10292 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x10293 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x10294 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x10298 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x10299 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x1029a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x1029b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x1029c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x1029d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x1029e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x1029f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x102a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x102a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x102a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x102a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x102a7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x102a8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x102a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x102aa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x102ab +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x102ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x102b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x102b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x102b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x102b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x102b4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x102b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x102b6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x102b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x102b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x102bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x102bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x102be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x102bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x102c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x102c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x102c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x102c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x102c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x102c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x102c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x102ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x102cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x102cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x102cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x102ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x102cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x102d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x102d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x102d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x102d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x102d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x102d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x102d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x102da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x102db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x102dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x102e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x102e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x102e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x102e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x102e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x102e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x102e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x102e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x102e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x10300 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x10301 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x10302 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x10303 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x10304 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x10305 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x10306 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x10307 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x10412 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x10413 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x10414 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x10414 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x10415 +#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x10455 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x10456 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x10457 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x10458 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x10459 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1045a +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x1045b +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x1045c +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x1045d +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x1045e +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x10462 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x10463 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x10464 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x10465 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x10480 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x10481 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x10482 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x10483 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x10484 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x10485 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x10486 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x10487 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x10488 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x10489 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x1048a +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x1048b +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x1048c +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x10492 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x10493 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x10494 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x10495 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x10496 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x10497 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x10497 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x104a8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x104a9 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x104a9 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x104b4 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x104b5 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x104b5 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x104ca +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x104cb +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x104cb +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 +#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +// base address: 0x10134000 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXTDEC +// base address: 0x10168000 +#define regPCIEMSIX_VECT0_ADDR_LO 0x1a000 +#define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT0_ADDR_HI 0x1a001 +#define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT0_MSG_DATA 0x1a002 +#define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT0_CONTROL 0x1a003 +#define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT1_ADDR_LO 0x1a004 +#define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT1_ADDR_HI 0x1a005 +#define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT1_MSG_DATA 0x1a006 +#define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT1_CONTROL 0x1a007 +#define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT2_ADDR_LO 0x1a008 +#define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT2_ADDR_HI 0x1a009 +#define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT2_MSG_DATA 0x1a00a +#define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT2_CONTROL 0x1a00b +#define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT3_ADDR_LO 0x1a00c +#define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT3_ADDR_HI 0x1a00d +#define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT3_MSG_DATA 0x1a00e +#define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT3_CONTROL 0x1a00f +#define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT4_ADDR_LO 0x1a010 +#define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT4_ADDR_HI 0x1a011 +#define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT4_MSG_DATA 0x1a012 +#define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT4_CONTROL 0x1a013 +#define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT5_ADDR_LO 0x1a014 +#define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT5_ADDR_HI 0x1a015 +#define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT5_MSG_DATA 0x1a016 +#define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT5_CONTROL 0x1a017 +#define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT6_ADDR_LO 0x1a018 +#define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT6_ADDR_HI 0x1a019 +#define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT6_MSG_DATA 0x1a01a +#define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT6_CONTROL 0x1a01b +#define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT7_ADDR_LO 0x1a01c +#define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT7_ADDR_HI 0x1a01d +#define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT7_MSG_DATA 0x1a01e +#define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT7_CONTROL 0x1a01f +#define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT8_ADDR_LO 0x1a020 +#define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT8_ADDR_HI 0x1a021 +#define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT8_MSG_DATA 0x1a022 +#define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT8_CONTROL 0x1a023 +#define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT9_ADDR_LO 0x1a024 +#define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT9_ADDR_HI 0x1a025 +#define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT9_MSG_DATA 0x1a026 +#define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT9_CONTROL 0x1a027 +#define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT10_ADDR_LO 0x1a028 +#define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT10_ADDR_HI 0x1a029 +#define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT10_MSG_DATA 0x1a02a +#define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT10_CONTROL 0x1a02b +#define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT11_ADDR_LO 0x1a02c +#define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT11_ADDR_HI 0x1a02d +#define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT11_MSG_DATA 0x1a02e +#define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT11_CONTROL 0x1a02f +#define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT12_ADDR_LO 0x1a030 +#define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT12_ADDR_HI 0x1a031 +#define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT12_MSG_DATA 0x1a032 +#define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT12_CONTROL 0x1a033 +#define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT13_ADDR_LO 0x1a034 +#define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT13_ADDR_HI 0x1a035 +#define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT13_MSG_DATA 0x1a036 +#define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT13_CONTROL 0x1a037 +#define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT14_ADDR_LO 0x1a038 +#define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT14_ADDR_HI 0x1a039 +#define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT14_MSG_DATA 0x1a03a +#define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT14_CONTROL 0x1a03b +#define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT15_ADDR_LO 0x1a03c +#define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT15_ADDR_HI 0x1a03d +#define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT15_MSG_DATA 0x1a03e +#define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT15_CONTROL 0x1a03f +#define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT16_ADDR_LO 0x1a040 +#define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT16_ADDR_HI 0x1a041 +#define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT16_MSG_DATA 0x1a042 +#define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT16_CONTROL 0x1a043 +#define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT17_ADDR_LO 0x1a044 +#define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT17_ADDR_HI 0x1a045 +#define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT17_MSG_DATA 0x1a046 +#define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT17_CONTROL 0x1a047 +#define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT18_ADDR_LO 0x1a048 +#define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT18_ADDR_HI 0x1a049 +#define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT18_MSG_DATA 0x1a04a +#define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT18_CONTROL 0x1a04b +#define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT19_ADDR_LO 0x1a04c +#define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT19_ADDR_HI 0x1a04d +#define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT19_MSG_DATA 0x1a04e +#define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT19_CONTROL 0x1a04f +#define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT20_ADDR_LO 0x1a050 +#define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT20_ADDR_HI 0x1a051 +#define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT20_MSG_DATA 0x1a052 +#define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT20_CONTROL 0x1a053 +#define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT21_ADDR_LO 0x1a054 +#define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT21_ADDR_HI 0x1a055 +#define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT21_MSG_DATA 0x1a056 +#define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT21_CONTROL 0x1a057 +#define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT22_ADDR_LO 0x1a058 +#define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT22_ADDR_HI 0x1a059 +#define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT22_MSG_DATA 0x1a05a +#define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT22_CONTROL 0x1a05b +#define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT23_ADDR_LO 0x1a05c +#define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT23_ADDR_HI 0x1a05d +#define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT23_MSG_DATA 0x1a05e +#define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT23_CONTROL 0x1a05f +#define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT24_ADDR_LO 0x1a060 +#define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT24_ADDR_HI 0x1a061 +#define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT24_MSG_DATA 0x1a062 +#define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT24_CONTROL 0x1a063 +#define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT25_ADDR_LO 0x1a064 +#define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT25_ADDR_HI 0x1a065 +#define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT25_MSG_DATA 0x1a066 +#define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT25_CONTROL 0x1a067 +#define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT26_ADDR_LO 0x1a068 +#define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT26_ADDR_HI 0x1a069 +#define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT26_MSG_DATA 0x1a06a +#define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT26_CONTROL 0x1a06b +#define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT27_ADDR_LO 0x1a06c +#define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT27_ADDR_HI 0x1a06d +#define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT27_MSG_DATA 0x1a06e +#define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT27_CONTROL 0x1a06f +#define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT28_ADDR_LO 0x1a070 +#define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT28_ADDR_HI 0x1a071 +#define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT28_MSG_DATA 0x1a072 +#define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT28_CONTROL 0x1a073 +#define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT29_ADDR_LO 0x1a074 +#define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT29_ADDR_HI 0x1a075 +#define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT29_MSG_DATA 0x1a076 +#define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT29_CONTROL 0x1a077 +#define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT30_ADDR_LO 0x1a078 +#define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT30_ADDR_HI 0x1a079 +#define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT30_MSG_DATA 0x1a07a +#define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT30_CONTROL 0x1a07b +#define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT31_ADDR_LO 0x1a07c +#define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT31_ADDR_HI 0x1a07d +#define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT31_MSG_DATA 0x1a07e +#define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT31_CONTROL 0x1a07f +#define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT32_ADDR_LO 0x1a080 +#define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT32_ADDR_HI 0x1a081 +#define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT32_MSG_DATA 0x1a082 +#define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT32_CONTROL 0x1a083 +#define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT33_ADDR_LO 0x1a084 +#define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT33_ADDR_HI 0x1a085 +#define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT33_MSG_DATA 0x1a086 +#define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT33_CONTROL 0x1a087 +#define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT34_ADDR_LO 0x1a088 +#define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT34_ADDR_HI 0x1a089 +#define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT34_MSG_DATA 0x1a08a +#define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT34_CONTROL 0x1a08b +#define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT35_ADDR_LO 0x1a08c +#define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT35_ADDR_HI 0x1a08d +#define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT35_MSG_DATA 0x1a08e +#define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT35_CONTROL 0x1a08f +#define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT36_ADDR_LO 0x1a090 +#define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT36_ADDR_HI 0x1a091 +#define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT36_MSG_DATA 0x1a092 +#define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT36_CONTROL 0x1a093 +#define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT37_ADDR_LO 0x1a094 +#define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT37_ADDR_HI 0x1a095 +#define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT37_MSG_DATA 0x1a096 +#define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT37_CONTROL 0x1a097 +#define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT38_ADDR_LO 0x1a098 +#define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT38_ADDR_HI 0x1a099 +#define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT38_MSG_DATA 0x1a09a +#define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT38_CONTROL 0x1a09b +#define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT39_ADDR_LO 0x1a09c +#define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT39_ADDR_HI 0x1a09d +#define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT39_MSG_DATA 0x1a09e +#define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT39_CONTROL 0x1a09f +#define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT40_ADDR_LO 0x1a0a0 +#define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT40_ADDR_HI 0x1a0a1 +#define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT40_MSG_DATA 0x1a0a2 +#define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT40_CONTROL 0x1a0a3 +#define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT41_ADDR_LO 0x1a0a4 +#define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT41_ADDR_HI 0x1a0a5 +#define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT41_MSG_DATA 0x1a0a6 +#define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT41_CONTROL 0x1a0a7 +#define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT42_ADDR_LO 0x1a0a8 +#define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT42_ADDR_HI 0x1a0a9 +#define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT42_MSG_DATA 0x1a0aa +#define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT42_CONTROL 0x1a0ab +#define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT43_ADDR_LO 0x1a0ac +#define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT43_ADDR_HI 0x1a0ad +#define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT43_MSG_DATA 0x1a0ae +#define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT43_CONTROL 0x1a0af +#define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT44_ADDR_LO 0x1a0b0 +#define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT44_ADDR_HI 0x1a0b1 +#define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT44_MSG_DATA 0x1a0b2 +#define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT44_CONTROL 0x1a0b3 +#define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT45_ADDR_LO 0x1a0b4 +#define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT45_ADDR_HI 0x1a0b5 +#define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT45_MSG_DATA 0x1a0b6 +#define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT45_CONTROL 0x1a0b7 +#define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT46_ADDR_LO 0x1a0b8 +#define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT46_ADDR_HI 0x1a0b9 +#define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT46_MSG_DATA 0x1a0ba +#define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT46_CONTROL 0x1a0bb +#define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT47_ADDR_LO 0x1a0bc +#define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT47_ADDR_HI 0x1a0bd +#define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT47_MSG_DATA 0x1a0be +#define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT47_CONTROL 0x1a0bf +#define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT48_ADDR_LO 0x1a0c0 +#define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT48_ADDR_HI 0x1a0c1 +#define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT48_MSG_DATA 0x1a0c2 +#define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT48_CONTROL 0x1a0c3 +#define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT49_ADDR_LO 0x1a0c4 +#define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT49_ADDR_HI 0x1a0c5 +#define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT49_MSG_DATA 0x1a0c6 +#define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT49_CONTROL 0x1a0c7 +#define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT50_ADDR_LO 0x1a0c8 +#define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT50_ADDR_HI 0x1a0c9 +#define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT50_MSG_DATA 0x1a0ca +#define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT50_CONTROL 0x1a0cb +#define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT51_ADDR_LO 0x1a0cc +#define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT51_ADDR_HI 0x1a0cd +#define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT51_MSG_DATA 0x1a0ce +#define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT51_CONTROL 0x1a0cf +#define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT52_ADDR_LO 0x1a0d0 +#define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT52_ADDR_HI 0x1a0d1 +#define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT52_MSG_DATA 0x1a0d2 +#define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT52_CONTROL 0x1a0d3 +#define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT53_ADDR_LO 0x1a0d4 +#define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT53_ADDR_HI 0x1a0d5 +#define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT53_MSG_DATA 0x1a0d6 +#define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT53_CONTROL 0x1a0d7 +#define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT54_ADDR_LO 0x1a0d8 +#define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT54_ADDR_HI 0x1a0d9 +#define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT54_MSG_DATA 0x1a0da +#define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT54_CONTROL 0x1a0db +#define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT55_ADDR_LO 0x1a0dc +#define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT55_ADDR_HI 0x1a0dd +#define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT55_MSG_DATA 0x1a0de +#define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT55_CONTROL 0x1a0df +#define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT56_ADDR_LO 0x1a0e0 +#define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT56_ADDR_HI 0x1a0e1 +#define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT56_MSG_DATA 0x1a0e2 +#define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT56_CONTROL 0x1a0e3 +#define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT57_ADDR_LO 0x1a0e4 +#define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT57_ADDR_HI 0x1a0e5 +#define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT57_MSG_DATA 0x1a0e6 +#define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT57_CONTROL 0x1a0e7 +#define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT58_ADDR_LO 0x1a0e8 +#define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT58_ADDR_HI 0x1a0e9 +#define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT58_MSG_DATA 0x1a0ea +#define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT58_CONTROL 0x1a0eb +#define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT59_ADDR_LO 0x1a0ec +#define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT59_ADDR_HI 0x1a0ed +#define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT59_MSG_DATA 0x1a0ee +#define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT59_CONTROL 0x1a0ef +#define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT60_ADDR_LO 0x1a0f0 +#define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT60_ADDR_HI 0x1a0f1 +#define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT60_MSG_DATA 0x1a0f2 +#define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT60_CONTROL 0x1a0f3 +#define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT61_ADDR_LO 0x1a0f4 +#define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT61_ADDR_HI 0x1a0f5 +#define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT61_MSG_DATA 0x1a0f6 +#define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT61_CONTROL 0x1a0f7 +#define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT62_ADDR_LO 0x1a0f8 +#define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT62_ADDR_HI 0x1a0f9 +#define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT62_MSG_DATA 0x1a0fa +#define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT62_CONTROL 0x1a0fb +#define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT63_ADDR_LO 0x1a0fc +#define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT63_ADDR_HI 0x1a0fd +#define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT63_MSG_DATA 0x1a0fe +#define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT63_CONTROL 0x1a0ff +#define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT64_ADDR_LO 0x1a100 +#define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT64_ADDR_HI 0x1a101 +#define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT64_MSG_DATA 0x1a102 +#define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT64_CONTROL 0x1a103 +#define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT65_ADDR_LO 0x1a104 +#define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT65_ADDR_HI 0x1a105 +#define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT65_MSG_DATA 0x1a106 +#define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT65_CONTROL 0x1a107 +#define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT66_ADDR_LO 0x1a108 +#define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT66_ADDR_HI 0x1a109 +#define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT66_MSG_DATA 0x1a10a +#define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT66_CONTROL 0x1a10b +#define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT67_ADDR_LO 0x1a10c +#define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT67_ADDR_HI 0x1a10d +#define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT67_MSG_DATA 0x1a10e +#define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT67_CONTROL 0x1a10f +#define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT68_ADDR_LO 0x1a110 +#define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT68_ADDR_HI 0x1a111 +#define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT68_MSG_DATA 0x1a112 +#define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT68_CONTROL 0x1a113 +#define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT69_ADDR_LO 0x1a114 +#define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT69_ADDR_HI 0x1a115 +#define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT69_MSG_DATA 0x1a116 +#define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT69_CONTROL 0x1a117 +#define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT70_ADDR_LO 0x1a118 +#define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT70_ADDR_HI 0x1a119 +#define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT70_MSG_DATA 0x1a11a +#define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT70_CONTROL 0x1a11b +#define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT71_ADDR_LO 0x1a11c +#define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT71_ADDR_HI 0x1a11d +#define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT71_MSG_DATA 0x1a11e +#define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT71_CONTROL 0x1a11f +#define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT72_ADDR_LO 0x1a120 +#define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT72_ADDR_HI 0x1a121 +#define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT72_MSG_DATA 0x1a122 +#define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT72_CONTROL 0x1a123 +#define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT73_ADDR_LO 0x1a124 +#define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT73_ADDR_HI 0x1a125 +#define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT73_MSG_DATA 0x1a126 +#define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT73_CONTROL 0x1a127 +#define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT74_ADDR_LO 0x1a128 +#define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT74_ADDR_HI 0x1a129 +#define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT74_MSG_DATA 0x1a12a +#define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT74_CONTROL 0x1a12b +#define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT75_ADDR_LO 0x1a12c +#define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT75_ADDR_HI 0x1a12d +#define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT75_MSG_DATA 0x1a12e +#define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT75_CONTROL 0x1a12f +#define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT76_ADDR_LO 0x1a130 +#define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT76_ADDR_HI 0x1a131 +#define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT76_MSG_DATA 0x1a132 +#define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT76_CONTROL 0x1a133 +#define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT77_ADDR_LO 0x1a134 +#define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT77_ADDR_HI 0x1a135 +#define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT77_MSG_DATA 0x1a136 +#define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT77_CONTROL 0x1a137 +#define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT78_ADDR_LO 0x1a138 +#define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT78_ADDR_HI 0x1a139 +#define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT78_MSG_DATA 0x1a13a +#define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT78_CONTROL 0x1a13b +#define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT79_ADDR_LO 0x1a13c +#define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT79_ADDR_HI 0x1a13d +#define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT79_MSG_DATA 0x1a13e +#define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT79_CONTROL 0x1a13f +#define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT80_ADDR_LO 0x1a140 +#define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT80_ADDR_HI 0x1a141 +#define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT80_MSG_DATA 0x1a142 +#define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT80_CONTROL 0x1a143 +#define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT81_ADDR_LO 0x1a144 +#define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT81_ADDR_HI 0x1a145 +#define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT81_MSG_DATA 0x1a146 +#define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT81_CONTROL 0x1a147 +#define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT82_ADDR_LO 0x1a148 +#define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT82_ADDR_HI 0x1a149 +#define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT82_MSG_DATA 0x1a14a +#define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT82_CONTROL 0x1a14b +#define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT83_ADDR_LO 0x1a14c +#define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT83_ADDR_HI 0x1a14d +#define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT83_MSG_DATA 0x1a14e +#define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT83_CONTROL 0x1a14f +#define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT84_ADDR_LO 0x1a150 +#define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT84_ADDR_HI 0x1a151 +#define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT84_MSG_DATA 0x1a152 +#define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT84_CONTROL 0x1a153 +#define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT85_ADDR_LO 0x1a154 +#define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT85_ADDR_HI 0x1a155 +#define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT85_MSG_DATA 0x1a156 +#define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT85_CONTROL 0x1a157 +#define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT86_ADDR_LO 0x1a158 +#define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT86_ADDR_HI 0x1a159 +#define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT86_MSG_DATA 0x1a15a +#define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT86_CONTROL 0x1a15b +#define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT87_ADDR_LO 0x1a15c +#define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT87_ADDR_HI 0x1a15d +#define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT87_MSG_DATA 0x1a15e +#define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT87_CONTROL 0x1a15f +#define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT88_ADDR_LO 0x1a160 +#define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT88_ADDR_HI 0x1a161 +#define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT88_MSG_DATA 0x1a162 +#define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT88_CONTROL 0x1a163 +#define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT89_ADDR_LO 0x1a164 +#define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT89_ADDR_HI 0x1a165 +#define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT89_MSG_DATA 0x1a166 +#define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT89_CONTROL 0x1a167 +#define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT90_ADDR_LO 0x1a168 +#define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT90_ADDR_HI 0x1a169 +#define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT90_MSG_DATA 0x1a16a +#define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT90_CONTROL 0x1a16b +#define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT91_ADDR_LO 0x1a16c +#define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT91_ADDR_HI 0x1a16d +#define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT91_MSG_DATA 0x1a16e +#define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT91_CONTROL 0x1a16f +#define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT92_ADDR_LO 0x1a170 +#define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT92_ADDR_HI 0x1a171 +#define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT92_MSG_DATA 0x1a172 +#define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT92_CONTROL 0x1a173 +#define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT93_ADDR_LO 0x1a174 +#define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT93_ADDR_HI 0x1a175 +#define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT93_MSG_DATA 0x1a176 +#define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT93_CONTROL 0x1a177 +#define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT94_ADDR_LO 0x1a178 +#define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT94_ADDR_HI 0x1a179 +#define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT94_MSG_DATA 0x1a17a +#define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT94_CONTROL 0x1a17b +#define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT95_ADDR_LO 0x1a17c +#define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT95_ADDR_HI 0x1a17d +#define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT95_MSG_DATA 0x1a17e +#define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT95_CONTROL 0x1a17f +#define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT96_ADDR_LO 0x1a180 +#define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT96_ADDR_HI 0x1a181 +#define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT96_MSG_DATA 0x1a182 +#define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT96_CONTROL 0x1a183 +#define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT97_ADDR_LO 0x1a184 +#define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT97_ADDR_HI 0x1a185 +#define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT97_MSG_DATA 0x1a186 +#define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT97_CONTROL 0x1a187 +#define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT98_ADDR_LO 0x1a188 +#define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT98_ADDR_HI 0x1a189 +#define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT98_MSG_DATA 0x1a18a +#define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT98_CONTROL 0x1a18b +#define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT99_ADDR_LO 0x1a18c +#define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT99_ADDR_HI 0x1a18d +#define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT99_MSG_DATA 0x1a18e +#define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT99_CONTROL 0x1a18f +#define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT100_ADDR_LO 0x1a190 +#define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT100_ADDR_HI 0x1a191 +#define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT100_MSG_DATA 0x1a192 +#define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT100_CONTROL 0x1a193 +#define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT101_ADDR_LO 0x1a194 +#define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT101_ADDR_HI 0x1a195 +#define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT101_MSG_DATA 0x1a196 +#define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT101_CONTROL 0x1a197 +#define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT102_ADDR_LO 0x1a198 +#define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT102_ADDR_HI 0x1a199 +#define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT102_MSG_DATA 0x1a19a +#define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT102_CONTROL 0x1a19b +#define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT103_ADDR_LO 0x1a19c +#define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT103_ADDR_HI 0x1a19d +#define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT103_MSG_DATA 0x1a19e +#define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT103_CONTROL 0x1a19f +#define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT104_ADDR_LO 0x1a1a0 +#define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT104_ADDR_HI 0x1a1a1 +#define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT104_MSG_DATA 0x1a1a2 +#define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT104_CONTROL 0x1a1a3 +#define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT105_ADDR_LO 0x1a1a4 +#define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT105_ADDR_HI 0x1a1a5 +#define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT105_MSG_DATA 0x1a1a6 +#define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT105_CONTROL 0x1a1a7 +#define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT106_ADDR_LO 0x1a1a8 +#define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT106_ADDR_HI 0x1a1a9 +#define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT106_MSG_DATA 0x1a1aa +#define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT106_CONTROL 0x1a1ab +#define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT107_ADDR_LO 0x1a1ac +#define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT107_ADDR_HI 0x1a1ad +#define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT107_MSG_DATA 0x1a1ae +#define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT107_CONTROL 0x1a1af +#define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT108_ADDR_LO 0x1a1b0 +#define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT108_ADDR_HI 0x1a1b1 +#define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT108_MSG_DATA 0x1a1b2 +#define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT108_CONTROL 0x1a1b3 +#define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT109_ADDR_LO 0x1a1b4 +#define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT109_ADDR_HI 0x1a1b5 +#define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT109_MSG_DATA 0x1a1b6 +#define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT109_CONTROL 0x1a1b7 +#define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT110_ADDR_LO 0x1a1b8 +#define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT110_ADDR_HI 0x1a1b9 +#define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT110_MSG_DATA 0x1a1ba +#define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT110_CONTROL 0x1a1bb +#define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT111_ADDR_LO 0x1a1bc +#define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT111_ADDR_HI 0x1a1bd +#define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT111_MSG_DATA 0x1a1be +#define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT111_CONTROL 0x1a1bf +#define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT112_ADDR_LO 0x1a1c0 +#define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT112_ADDR_HI 0x1a1c1 +#define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT112_MSG_DATA 0x1a1c2 +#define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT112_CONTROL 0x1a1c3 +#define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT113_ADDR_LO 0x1a1c4 +#define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT113_ADDR_HI 0x1a1c5 +#define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT113_MSG_DATA 0x1a1c6 +#define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT113_CONTROL 0x1a1c7 +#define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT114_ADDR_LO 0x1a1c8 +#define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT114_ADDR_HI 0x1a1c9 +#define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT114_MSG_DATA 0x1a1ca +#define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT114_CONTROL 0x1a1cb +#define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT115_ADDR_LO 0x1a1cc +#define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT115_ADDR_HI 0x1a1cd +#define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT115_MSG_DATA 0x1a1ce +#define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT115_CONTROL 0x1a1cf +#define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT116_ADDR_LO 0x1a1d0 +#define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT116_ADDR_HI 0x1a1d1 +#define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT116_MSG_DATA 0x1a1d2 +#define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT116_CONTROL 0x1a1d3 +#define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT117_ADDR_LO 0x1a1d4 +#define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT117_ADDR_HI 0x1a1d5 +#define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT117_MSG_DATA 0x1a1d6 +#define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT117_CONTROL 0x1a1d7 +#define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT118_ADDR_LO 0x1a1d8 +#define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT118_ADDR_HI 0x1a1d9 +#define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT118_MSG_DATA 0x1a1da +#define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT118_CONTROL 0x1a1db +#define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT119_ADDR_LO 0x1a1dc +#define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT119_ADDR_HI 0x1a1dd +#define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT119_MSG_DATA 0x1a1de +#define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT119_CONTROL 0x1a1df +#define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT120_ADDR_LO 0x1a1e0 +#define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT120_ADDR_HI 0x1a1e1 +#define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT120_MSG_DATA 0x1a1e2 +#define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT120_CONTROL 0x1a1e3 +#define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT121_ADDR_LO 0x1a1e4 +#define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT121_ADDR_HI 0x1a1e5 +#define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT121_MSG_DATA 0x1a1e6 +#define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT121_CONTROL 0x1a1e7 +#define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT122_ADDR_LO 0x1a1e8 +#define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT122_ADDR_HI 0x1a1e9 +#define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT122_MSG_DATA 0x1a1ea +#define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT122_CONTROL 0x1a1eb +#define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT123_ADDR_LO 0x1a1ec +#define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT123_ADDR_HI 0x1a1ed +#define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT123_MSG_DATA 0x1a1ee +#define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT123_CONTROL 0x1a1ef +#define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT124_ADDR_LO 0x1a1f0 +#define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT124_ADDR_HI 0x1a1f1 +#define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT124_MSG_DATA 0x1a1f2 +#define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT124_CONTROL 0x1a1f3 +#define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT125_ADDR_LO 0x1a1f4 +#define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT125_ADDR_HI 0x1a1f5 +#define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT125_MSG_DATA 0x1a1f6 +#define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT125_CONTROL 0x1a1f7 +#define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT126_ADDR_LO 0x1a1f8 +#define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT126_ADDR_HI 0x1a1f9 +#define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT126_MSG_DATA 0x1a1fa +#define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT126_CONTROL 0x1a1fb +#define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT127_ADDR_LO 0x1a1fc +#define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT127_ADDR_HI 0x1a1fd +#define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT127_MSG_DATA 0x1a1fe +#define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT127_CONTROL 0x1a1ff +#define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT128_ADDR_LO 0x1a200 +#define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT128_ADDR_HI 0x1a201 +#define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT128_MSG_DATA 0x1a202 +#define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT128_CONTROL 0x1a203 +#define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT129_ADDR_LO 0x1a204 +#define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT129_ADDR_HI 0x1a205 +#define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT129_MSG_DATA 0x1a206 +#define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT129_CONTROL 0x1a207 +#define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT130_ADDR_LO 0x1a208 +#define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT130_ADDR_HI 0x1a209 +#define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT130_MSG_DATA 0x1a20a +#define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT130_CONTROL 0x1a20b +#define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT131_ADDR_LO 0x1a20c +#define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT131_ADDR_HI 0x1a20d +#define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT131_MSG_DATA 0x1a20e +#define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT131_CONTROL 0x1a20f +#define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT132_ADDR_LO 0x1a210 +#define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT132_ADDR_HI 0x1a211 +#define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT132_MSG_DATA 0x1a212 +#define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT132_CONTROL 0x1a213 +#define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT133_ADDR_LO 0x1a214 +#define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT133_ADDR_HI 0x1a215 +#define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT133_MSG_DATA 0x1a216 +#define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT133_CONTROL 0x1a217 +#define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT134_ADDR_LO 0x1a218 +#define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT134_ADDR_HI 0x1a219 +#define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT134_MSG_DATA 0x1a21a +#define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT134_CONTROL 0x1a21b +#define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT135_ADDR_LO 0x1a21c +#define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT135_ADDR_HI 0x1a21d +#define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT135_MSG_DATA 0x1a21e +#define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT135_CONTROL 0x1a21f +#define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT136_ADDR_LO 0x1a220 +#define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT136_ADDR_HI 0x1a221 +#define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT136_MSG_DATA 0x1a222 +#define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT136_CONTROL 0x1a223 +#define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT137_ADDR_LO 0x1a224 +#define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT137_ADDR_HI 0x1a225 +#define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT137_MSG_DATA 0x1a226 +#define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT137_CONTROL 0x1a227 +#define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT138_ADDR_LO 0x1a228 +#define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT138_ADDR_HI 0x1a229 +#define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT138_MSG_DATA 0x1a22a +#define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT138_CONTROL 0x1a22b +#define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT139_ADDR_LO 0x1a22c +#define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT139_ADDR_HI 0x1a22d +#define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT139_MSG_DATA 0x1a22e +#define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT139_CONTROL 0x1a22f +#define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT140_ADDR_LO 0x1a230 +#define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT140_ADDR_HI 0x1a231 +#define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT140_MSG_DATA 0x1a232 +#define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT140_CONTROL 0x1a233 +#define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT141_ADDR_LO 0x1a234 +#define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT141_ADDR_HI 0x1a235 +#define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT141_MSG_DATA 0x1a236 +#define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT141_CONTROL 0x1a237 +#define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT142_ADDR_LO 0x1a238 +#define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT142_ADDR_HI 0x1a239 +#define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT142_MSG_DATA 0x1a23a +#define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT142_CONTROL 0x1a23b +#define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT143_ADDR_LO 0x1a23c +#define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT143_ADDR_HI 0x1a23d +#define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT143_MSG_DATA 0x1a23e +#define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT143_CONTROL 0x1a23f +#define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT144_ADDR_LO 0x1a240 +#define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT144_ADDR_HI 0x1a241 +#define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT144_MSG_DATA 0x1a242 +#define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT144_CONTROL 0x1a243 +#define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT145_ADDR_LO 0x1a244 +#define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT145_ADDR_HI 0x1a245 +#define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT145_MSG_DATA 0x1a246 +#define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT145_CONTROL 0x1a247 +#define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT146_ADDR_LO 0x1a248 +#define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT146_ADDR_HI 0x1a249 +#define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT146_MSG_DATA 0x1a24a +#define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT146_CONTROL 0x1a24b +#define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT147_ADDR_LO 0x1a24c +#define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT147_ADDR_HI 0x1a24d +#define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT147_MSG_DATA 0x1a24e +#define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT147_CONTROL 0x1a24f +#define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT148_ADDR_LO 0x1a250 +#define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT148_ADDR_HI 0x1a251 +#define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT148_MSG_DATA 0x1a252 +#define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT148_CONTROL 0x1a253 +#define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT149_ADDR_LO 0x1a254 +#define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT149_ADDR_HI 0x1a255 +#define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT149_MSG_DATA 0x1a256 +#define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT149_CONTROL 0x1a257 +#define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT150_ADDR_LO 0x1a258 +#define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT150_ADDR_HI 0x1a259 +#define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT150_MSG_DATA 0x1a25a +#define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT150_CONTROL 0x1a25b +#define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT151_ADDR_LO 0x1a25c +#define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT151_ADDR_HI 0x1a25d +#define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT151_MSG_DATA 0x1a25e +#define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT151_CONTROL 0x1a25f +#define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT152_ADDR_LO 0x1a260 +#define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT152_ADDR_HI 0x1a261 +#define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT152_MSG_DATA 0x1a262 +#define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT152_CONTROL 0x1a263 +#define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT153_ADDR_LO 0x1a264 +#define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT153_ADDR_HI 0x1a265 +#define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT153_MSG_DATA 0x1a266 +#define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT153_CONTROL 0x1a267 +#define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT154_ADDR_LO 0x1a268 +#define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT154_ADDR_HI 0x1a269 +#define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT154_MSG_DATA 0x1a26a +#define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT154_CONTROL 0x1a26b +#define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT155_ADDR_LO 0x1a26c +#define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT155_ADDR_HI 0x1a26d +#define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT155_MSG_DATA 0x1a26e +#define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT155_CONTROL 0x1a26f +#define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT156_ADDR_LO 0x1a270 +#define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT156_ADDR_HI 0x1a271 +#define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT156_MSG_DATA 0x1a272 +#define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT156_CONTROL 0x1a273 +#define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT157_ADDR_LO 0x1a274 +#define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT157_ADDR_HI 0x1a275 +#define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT157_MSG_DATA 0x1a276 +#define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT157_CONTROL 0x1a277 +#define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT158_ADDR_LO 0x1a278 +#define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT158_ADDR_HI 0x1a279 +#define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT158_MSG_DATA 0x1a27a +#define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT158_CONTROL 0x1a27b +#define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT159_ADDR_LO 0x1a27c +#define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT159_ADDR_HI 0x1a27d +#define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT159_MSG_DATA 0x1a27e +#define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT159_CONTROL 0x1a27f +#define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT160_ADDR_LO 0x1a280 +#define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT160_ADDR_HI 0x1a281 +#define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT160_MSG_DATA 0x1a282 +#define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT160_CONTROL 0x1a283 +#define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT161_ADDR_LO 0x1a284 +#define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT161_ADDR_HI 0x1a285 +#define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT161_MSG_DATA 0x1a286 +#define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT161_CONTROL 0x1a287 +#define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT162_ADDR_LO 0x1a288 +#define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT162_ADDR_HI 0x1a289 +#define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT162_MSG_DATA 0x1a28a +#define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT162_CONTROL 0x1a28b +#define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT163_ADDR_LO 0x1a28c +#define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT163_ADDR_HI 0x1a28d +#define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT163_MSG_DATA 0x1a28e +#define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT163_CONTROL 0x1a28f +#define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT164_ADDR_LO 0x1a290 +#define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT164_ADDR_HI 0x1a291 +#define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT164_MSG_DATA 0x1a292 +#define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT164_CONTROL 0x1a293 +#define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT165_ADDR_LO 0x1a294 +#define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT165_ADDR_HI 0x1a295 +#define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT165_MSG_DATA 0x1a296 +#define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT165_CONTROL 0x1a297 +#define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT166_ADDR_LO 0x1a298 +#define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT166_ADDR_HI 0x1a299 +#define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT166_MSG_DATA 0x1a29a +#define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT166_CONTROL 0x1a29b +#define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT167_ADDR_LO 0x1a29c +#define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT167_ADDR_HI 0x1a29d +#define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT167_MSG_DATA 0x1a29e +#define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT167_CONTROL 0x1a29f +#define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT168_ADDR_LO 0x1a2a0 +#define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT168_ADDR_HI 0x1a2a1 +#define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT168_MSG_DATA 0x1a2a2 +#define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT168_CONTROL 0x1a2a3 +#define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT169_ADDR_LO 0x1a2a4 +#define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT169_ADDR_HI 0x1a2a5 +#define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT169_MSG_DATA 0x1a2a6 +#define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT169_CONTROL 0x1a2a7 +#define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT170_ADDR_LO 0x1a2a8 +#define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT170_ADDR_HI 0x1a2a9 +#define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT170_MSG_DATA 0x1a2aa +#define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT170_CONTROL 0x1a2ab +#define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT171_ADDR_LO 0x1a2ac +#define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT171_ADDR_HI 0x1a2ad +#define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT171_MSG_DATA 0x1a2ae +#define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT171_CONTROL 0x1a2af +#define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT172_ADDR_LO 0x1a2b0 +#define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT172_ADDR_HI 0x1a2b1 +#define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT172_MSG_DATA 0x1a2b2 +#define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT172_CONTROL 0x1a2b3 +#define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT173_ADDR_LO 0x1a2b4 +#define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT173_ADDR_HI 0x1a2b5 +#define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT173_MSG_DATA 0x1a2b6 +#define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT173_CONTROL 0x1a2b7 +#define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT174_ADDR_LO 0x1a2b8 +#define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT174_ADDR_HI 0x1a2b9 +#define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT174_MSG_DATA 0x1a2ba +#define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT174_CONTROL 0x1a2bb +#define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT175_ADDR_LO 0x1a2bc +#define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT175_ADDR_HI 0x1a2bd +#define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT175_MSG_DATA 0x1a2be +#define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT175_CONTROL 0x1a2bf +#define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT176_ADDR_LO 0x1a2c0 +#define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT176_ADDR_HI 0x1a2c1 +#define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT176_MSG_DATA 0x1a2c2 +#define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT176_CONTROL 0x1a2c3 +#define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT177_ADDR_LO 0x1a2c4 +#define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT177_ADDR_HI 0x1a2c5 +#define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT177_MSG_DATA 0x1a2c6 +#define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT177_CONTROL 0x1a2c7 +#define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT178_ADDR_LO 0x1a2c8 +#define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT178_ADDR_HI 0x1a2c9 +#define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT178_MSG_DATA 0x1a2ca +#define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT178_CONTROL 0x1a2cb +#define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT179_ADDR_LO 0x1a2cc +#define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT179_ADDR_HI 0x1a2cd +#define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT179_MSG_DATA 0x1a2ce +#define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT179_CONTROL 0x1a2cf +#define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT180_ADDR_LO 0x1a2d0 +#define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT180_ADDR_HI 0x1a2d1 +#define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT180_MSG_DATA 0x1a2d2 +#define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT180_CONTROL 0x1a2d3 +#define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT181_ADDR_LO 0x1a2d4 +#define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT181_ADDR_HI 0x1a2d5 +#define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT181_MSG_DATA 0x1a2d6 +#define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT181_CONTROL 0x1a2d7 +#define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT182_ADDR_LO 0x1a2d8 +#define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT182_ADDR_HI 0x1a2d9 +#define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT182_MSG_DATA 0x1a2da +#define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT182_CONTROL 0x1a2db +#define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT183_ADDR_LO 0x1a2dc +#define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT183_ADDR_HI 0x1a2dd +#define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT183_MSG_DATA 0x1a2de +#define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT183_CONTROL 0x1a2df +#define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT184_ADDR_LO 0x1a2e0 +#define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT184_ADDR_HI 0x1a2e1 +#define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT184_MSG_DATA 0x1a2e2 +#define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT184_CONTROL 0x1a2e3 +#define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT185_ADDR_LO 0x1a2e4 +#define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT185_ADDR_HI 0x1a2e5 +#define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT185_MSG_DATA 0x1a2e6 +#define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT185_CONTROL 0x1a2e7 +#define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT186_ADDR_LO 0x1a2e8 +#define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT186_ADDR_HI 0x1a2e9 +#define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT186_MSG_DATA 0x1a2ea +#define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT186_CONTROL 0x1a2eb +#define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT187_ADDR_LO 0x1a2ec +#define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT187_ADDR_HI 0x1a2ed +#define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT187_MSG_DATA 0x1a2ee +#define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT187_CONTROL 0x1a2ef +#define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT188_ADDR_LO 0x1a2f0 +#define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT188_ADDR_HI 0x1a2f1 +#define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT188_MSG_DATA 0x1a2f2 +#define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT188_CONTROL 0x1a2f3 +#define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT189_ADDR_LO 0x1a2f4 +#define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT189_ADDR_HI 0x1a2f5 +#define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT189_MSG_DATA 0x1a2f6 +#define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT189_CONTROL 0x1a2f7 +#define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT190_ADDR_LO 0x1a2f8 +#define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT190_ADDR_HI 0x1a2f9 +#define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT190_MSG_DATA 0x1a2fa +#define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT190_CONTROL 0x1a2fb +#define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT191_ADDR_LO 0x1a2fc +#define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT191_ADDR_HI 0x1a2fd +#define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT191_MSG_DATA 0x1a2fe +#define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT191_CONTROL 0x1a2ff +#define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT192_ADDR_LO 0x1a300 +#define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT192_ADDR_HI 0x1a301 +#define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT192_MSG_DATA 0x1a302 +#define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT192_CONTROL 0x1a303 +#define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT193_ADDR_LO 0x1a304 +#define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT193_ADDR_HI 0x1a305 +#define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT193_MSG_DATA 0x1a306 +#define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT193_CONTROL 0x1a307 +#define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT194_ADDR_LO 0x1a308 +#define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT194_ADDR_HI 0x1a309 +#define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT194_MSG_DATA 0x1a30a +#define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT194_CONTROL 0x1a30b +#define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT195_ADDR_LO 0x1a30c +#define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT195_ADDR_HI 0x1a30d +#define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT195_MSG_DATA 0x1a30e +#define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT195_CONTROL 0x1a30f +#define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT196_ADDR_LO 0x1a310 +#define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT196_ADDR_HI 0x1a311 +#define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT196_MSG_DATA 0x1a312 +#define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT196_CONTROL 0x1a313 +#define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT197_ADDR_LO 0x1a314 +#define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT197_ADDR_HI 0x1a315 +#define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT197_MSG_DATA 0x1a316 +#define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT197_CONTROL 0x1a317 +#define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT198_ADDR_LO 0x1a318 +#define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT198_ADDR_HI 0x1a319 +#define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT198_MSG_DATA 0x1a31a +#define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT198_CONTROL 0x1a31b +#define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT199_ADDR_LO 0x1a31c +#define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT199_ADDR_HI 0x1a31d +#define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT199_MSG_DATA 0x1a31e +#define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT199_CONTROL 0x1a31f +#define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT200_ADDR_LO 0x1a320 +#define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT200_ADDR_HI 0x1a321 +#define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT200_MSG_DATA 0x1a322 +#define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT200_CONTROL 0x1a323 +#define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT201_ADDR_LO 0x1a324 +#define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT201_ADDR_HI 0x1a325 +#define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT201_MSG_DATA 0x1a326 +#define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT201_CONTROL 0x1a327 +#define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT202_ADDR_LO 0x1a328 +#define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT202_ADDR_HI 0x1a329 +#define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT202_MSG_DATA 0x1a32a +#define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT202_CONTROL 0x1a32b +#define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT203_ADDR_LO 0x1a32c +#define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT203_ADDR_HI 0x1a32d +#define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT203_MSG_DATA 0x1a32e +#define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT203_CONTROL 0x1a32f +#define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT204_ADDR_LO 0x1a330 +#define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT204_ADDR_HI 0x1a331 +#define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT204_MSG_DATA 0x1a332 +#define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT204_CONTROL 0x1a333 +#define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT205_ADDR_LO 0x1a334 +#define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT205_ADDR_HI 0x1a335 +#define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT205_MSG_DATA 0x1a336 +#define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT205_CONTROL 0x1a337 +#define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT206_ADDR_LO 0x1a338 +#define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT206_ADDR_HI 0x1a339 +#define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT206_MSG_DATA 0x1a33a +#define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT206_CONTROL 0x1a33b +#define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT207_ADDR_LO 0x1a33c +#define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT207_ADDR_HI 0x1a33d +#define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT207_MSG_DATA 0x1a33e +#define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT207_CONTROL 0x1a33f +#define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT208_ADDR_LO 0x1a340 +#define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT208_ADDR_HI 0x1a341 +#define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT208_MSG_DATA 0x1a342 +#define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT208_CONTROL 0x1a343 +#define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT209_ADDR_LO 0x1a344 +#define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT209_ADDR_HI 0x1a345 +#define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT209_MSG_DATA 0x1a346 +#define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT209_CONTROL 0x1a347 +#define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT210_ADDR_LO 0x1a348 +#define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT210_ADDR_HI 0x1a349 +#define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT210_MSG_DATA 0x1a34a +#define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT210_CONTROL 0x1a34b +#define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT211_ADDR_LO 0x1a34c +#define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT211_ADDR_HI 0x1a34d +#define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT211_MSG_DATA 0x1a34e +#define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT211_CONTROL 0x1a34f +#define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT212_ADDR_LO 0x1a350 +#define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT212_ADDR_HI 0x1a351 +#define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT212_MSG_DATA 0x1a352 +#define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT212_CONTROL 0x1a353 +#define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT213_ADDR_LO 0x1a354 +#define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT213_ADDR_HI 0x1a355 +#define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT213_MSG_DATA 0x1a356 +#define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT213_CONTROL 0x1a357 +#define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT214_ADDR_LO 0x1a358 +#define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT214_ADDR_HI 0x1a359 +#define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT214_MSG_DATA 0x1a35a +#define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT214_CONTROL 0x1a35b +#define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT215_ADDR_LO 0x1a35c +#define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT215_ADDR_HI 0x1a35d +#define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT215_MSG_DATA 0x1a35e +#define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT215_CONTROL 0x1a35f +#define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT216_ADDR_LO 0x1a360 +#define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT216_ADDR_HI 0x1a361 +#define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT216_MSG_DATA 0x1a362 +#define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT216_CONTROL 0x1a363 +#define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT217_ADDR_LO 0x1a364 +#define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT217_ADDR_HI 0x1a365 +#define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT217_MSG_DATA 0x1a366 +#define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT217_CONTROL 0x1a367 +#define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT218_ADDR_LO 0x1a368 +#define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT218_ADDR_HI 0x1a369 +#define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT218_MSG_DATA 0x1a36a +#define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT218_CONTROL 0x1a36b +#define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT219_ADDR_LO 0x1a36c +#define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT219_ADDR_HI 0x1a36d +#define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT219_MSG_DATA 0x1a36e +#define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT219_CONTROL 0x1a36f +#define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT220_ADDR_LO 0x1a370 +#define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT220_ADDR_HI 0x1a371 +#define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT220_MSG_DATA 0x1a372 +#define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT220_CONTROL 0x1a373 +#define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT221_ADDR_LO 0x1a374 +#define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT221_ADDR_HI 0x1a375 +#define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT221_MSG_DATA 0x1a376 +#define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT221_CONTROL 0x1a377 +#define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT222_ADDR_LO 0x1a378 +#define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT222_ADDR_HI 0x1a379 +#define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT222_MSG_DATA 0x1a37a +#define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT222_CONTROL 0x1a37b +#define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT223_ADDR_LO 0x1a37c +#define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT223_ADDR_HI 0x1a37d +#define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT223_MSG_DATA 0x1a37e +#define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT223_CONTROL 0x1a37f +#define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT224_ADDR_LO 0x1a380 +#define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT224_ADDR_HI 0x1a381 +#define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT224_MSG_DATA 0x1a382 +#define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT224_CONTROL 0x1a383 +#define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT225_ADDR_LO 0x1a384 +#define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT225_ADDR_HI 0x1a385 +#define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT225_MSG_DATA 0x1a386 +#define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT225_CONTROL 0x1a387 +#define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT226_ADDR_LO 0x1a388 +#define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT226_ADDR_HI 0x1a389 +#define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT226_MSG_DATA 0x1a38a +#define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT226_CONTROL 0x1a38b +#define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT227_ADDR_LO 0x1a38c +#define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT227_ADDR_HI 0x1a38d +#define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT227_MSG_DATA 0x1a38e +#define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT227_CONTROL 0x1a38f +#define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT228_ADDR_LO 0x1a390 +#define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT228_ADDR_HI 0x1a391 +#define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT228_MSG_DATA 0x1a392 +#define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT228_CONTROL 0x1a393 +#define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT229_ADDR_LO 0x1a394 +#define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT229_ADDR_HI 0x1a395 +#define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT229_MSG_DATA 0x1a396 +#define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT229_CONTROL 0x1a397 +#define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT230_ADDR_LO 0x1a398 +#define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT230_ADDR_HI 0x1a399 +#define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT230_MSG_DATA 0x1a39a +#define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT230_CONTROL 0x1a39b +#define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT231_ADDR_LO 0x1a39c +#define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT231_ADDR_HI 0x1a39d +#define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT231_MSG_DATA 0x1a39e +#define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT231_CONTROL 0x1a39f +#define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT232_ADDR_LO 0x1a3a0 +#define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT232_ADDR_HI 0x1a3a1 +#define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT232_MSG_DATA 0x1a3a2 +#define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT232_CONTROL 0x1a3a3 +#define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT233_ADDR_LO 0x1a3a4 +#define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT233_ADDR_HI 0x1a3a5 +#define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT233_MSG_DATA 0x1a3a6 +#define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT233_CONTROL 0x1a3a7 +#define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT234_ADDR_LO 0x1a3a8 +#define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT234_ADDR_HI 0x1a3a9 +#define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT234_MSG_DATA 0x1a3aa +#define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT234_CONTROL 0x1a3ab +#define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT235_ADDR_LO 0x1a3ac +#define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT235_ADDR_HI 0x1a3ad +#define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT235_MSG_DATA 0x1a3ae +#define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT235_CONTROL 0x1a3af +#define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT236_ADDR_LO 0x1a3b0 +#define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT236_ADDR_HI 0x1a3b1 +#define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT236_MSG_DATA 0x1a3b2 +#define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT236_CONTROL 0x1a3b3 +#define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT237_ADDR_LO 0x1a3b4 +#define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT237_ADDR_HI 0x1a3b5 +#define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT237_MSG_DATA 0x1a3b6 +#define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT237_CONTROL 0x1a3b7 +#define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT238_ADDR_LO 0x1a3b8 +#define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT238_ADDR_HI 0x1a3b9 +#define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT238_MSG_DATA 0x1a3ba +#define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT238_CONTROL 0x1a3bb +#define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT239_ADDR_LO 0x1a3bc +#define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT239_ADDR_HI 0x1a3bd +#define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT239_MSG_DATA 0x1a3be +#define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT239_CONTROL 0x1a3bf +#define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT240_ADDR_LO 0x1a3c0 +#define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT240_ADDR_HI 0x1a3c1 +#define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT240_MSG_DATA 0x1a3c2 +#define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT240_CONTROL 0x1a3c3 +#define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT241_ADDR_LO 0x1a3c4 +#define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT241_ADDR_HI 0x1a3c5 +#define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT241_MSG_DATA 0x1a3c6 +#define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT241_CONTROL 0x1a3c7 +#define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT242_ADDR_LO 0x1a3c8 +#define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT242_ADDR_HI 0x1a3c9 +#define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT242_MSG_DATA 0x1a3ca +#define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT242_CONTROL 0x1a3cb +#define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT243_ADDR_LO 0x1a3cc +#define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT243_ADDR_HI 0x1a3cd +#define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT243_MSG_DATA 0x1a3ce +#define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT243_CONTROL 0x1a3cf +#define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT244_ADDR_LO 0x1a3d0 +#define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT244_ADDR_HI 0x1a3d1 +#define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT244_MSG_DATA 0x1a3d2 +#define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT244_CONTROL 0x1a3d3 +#define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT245_ADDR_LO 0x1a3d4 +#define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT245_ADDR_HI 0x1a3d5 +#define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT245_MSG_DATA 0x1a3d6 +#define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT245_CONTROL 0x1a3d7 +#define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT246_ADDR_LO 0x1a3d8 +#define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT246_ADDR_HI 0x1a3d9 +#define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT246_MSG_DATA 0x1a3da +#define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT246_CONTROL 0x1a3db +#define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT247_ADDR_LO 0x1a3dc +#define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT247_ADDR_HI 0x1a3dd +#define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT247_MSG_DATA 0x1a3de +#define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT247_CONTROL 0x1a3df +#define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT248_ADDR_LO 0x1a3e0 +#define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT248_ADDR_HI 0x1a3e1 +#define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT248_MSG_DATA 0x1a3e2 +#define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT248_CONTROL 0x1a3e3 +#define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT249_ADDR_LO 0x1a3e4 +#define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT249_ADDR_HI 0x1a3e5 +#define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT249_MSG_DATA 0x1a3e6 +#define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT249_CONTROL 0x1a3e7 +#define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT250_ADDR_LO 0x1a3e8 +#define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT250_ADDR_HI 0x1a3e9 +#define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT250_MSG_DATA 0x1a3ea +#define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT250_CONTROL 0x1a3eb +#define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT251_ADDR_LO 0x1a3ec +#define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT251_ADDR_HI 0x1a3ed +#define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT251_MSG_DATA 0x1a3ee +#define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT251_CONTROL 0x1a3ef +#define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT252_ADDR_LO 0x1a3f0 +#define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT252_ADDR_HI 0x1a3f1 +#define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT252_MSG_DATA 0x1a3f2 +#define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT252_CONTROL 0x1a3f3 +#define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT253_ADDR_LO 0x1a3f4 +#define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT253_ADDR_HI 0x1a3f5 +#define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT253_MSG_DATA 0x1a3f6 +#define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT253_CONTROL 0x1a3f7 +#define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT254_ADDR_LO 0x1a3f8 +#define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT254_ADDR_HI 0x1a3f9 +#define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT254_MSG_DATA 0x1a3fa +#define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT254_CONTROL 0x1a3fb +#define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT255_ADDR_LO 0x1a3fc +#define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT255_ADDR_HI 0x1a3fd +#define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT255_MSG_DATA 0x1a3fe +#define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT255_CONTROL 0x1a3ff +#define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXPDEC +// base address: 0x10169000 +#define regPCIEMSIX_PBA_0 0x1a400 +#define regPCIEMSIX_PBA_0_BASE_IDX 8 +#define regPCIEMSIX_PBA_1 0x1a401 +#define regPCIEMSIX_PBA_1_BASE_IDX 8 +#define regPCIEMSIX_PBA_2 0x1a402 +#define regPCIEMSIX_PBA_2_BASE_IDX 8 +#define regPCIEMSIX_PBA_3 0x1a403 +#define regPCIEMSIX_PBA_3_BASE_IDX 8 +#define regPCIEMSIX_PBA_4 0x1a404 +#define regPCIEMSIX_PBA_4_BASE_IDX 8 +#define regPCIEMSIX_PBA_5 0x1a405 +#define regPCIEMSIX_PBA_5_BASE_IDX 8 +#define regPCIEMSIX_PBA_6 0x1a406 +#define regPCIEMSIX_PBA_6_BASE_IDX 8 +#define regPCIEMSIX_PBA_7 0x1a407 +#define regPCIEMSIX_PBA_7_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_swus_SUMDEC +// base address: 0x1013b000 +#define regSUM_INDEX 0xec38 +#define regSUM_INDEX_BASE_IDX 8 +#define regSUM_DATA 0xec39 +#define regSUM_DATA_BASE_IDX 8 +#define regSUM_INDEX_HI 0xec3b +#define regSUM_INDEX_HI_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP0 0xc480 +#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP1 0xc481 +#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP2 0xc482 +#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP3 0xc483 +#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP4 0xc484 +#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP5 0xc485 +#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP6 0xc486 +#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP7 0xc487 +#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP8 0xc488 +#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP9 0xc489 +#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP10 0xc48a +#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP11 0xc48b +#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP12 0xc48c +#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP13 0xc48d +#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP14 0xc48e +#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP0 0xc500 +#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP1 0xc501 +#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP2 0xc502 +#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP3 0xc503 +#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP4 0xc504 +#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP5 0xc505 +#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP6 0xc506 +#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP7 0xc507 +#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP8 0xc508 +#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP9 0xc509 +#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP10 0xc50a +#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP11 0xc50b +#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP12 0xc50c +#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP13 0xc50d +#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP14 0xc50e +#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 +#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 +#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 +#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 +#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 +#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 +#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 +#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP0 0xd100 +#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP2 0xd102 +#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP3 0xd103 +#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP4 0xd104 +#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP5 0xd105 +#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP6 0xd106 +#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP7 0xd107 +#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP10 0xd10a +#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP11 0xd10b +#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP12 0xd10c +#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP13 0xd10d +#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP14 0xd10e +#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP20 0xd114 +#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP0 0xd180 +#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP2 0xd182 +#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP3 0xd183 +#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP4 0xd184 +#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP5 0xd185 +#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP6 0xd186 +#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP7 0xd187 +#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP10 0xd18a +#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP11 0xd18b +#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP12 0xd18c +#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP13 0xd18d +#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP14 0xd18e +#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP20 0xd194 +#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP0 0xd200 +#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP2 0xd202 +#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP3 0xd203 +#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP4 0xd204 +#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP5 0xd205 +#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP6 0xd206 +#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP7 0xd207 +#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP13 0xd20d +#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP14 0xd20e +#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP0 0xd280 +#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP2 0xd282 +#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP3 0xd283 +#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP4 0xd284 +#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP5 0xd285 +#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP6 0xd286 +#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP7 0xd287 +#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP13 0xd28d +#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP14 0xd28e +#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP0 0xd300 +#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP2 0xd302 +#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP3 0xd303 +#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP4 0xd304 +#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP5 0xd305 +#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP6 0xd306 +#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP13 0xd30d +#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP14 0xd30e +#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP0 0xd380 +#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP2 0xd382 +#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP3 0xd383 +#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP4 0xd384 +#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP5 0xd385 +#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP6 0xd386 +#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP7 0xd387 +#define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP13 0xd38d +#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP14 0xd38e +#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP0 0xd400 +#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP2 0xd402 +#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP3 0xd403 +#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP4 0xd404 +#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP5 0xd405 +#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP6 0xd406 +#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP7 0xd407 +#define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP13 0xd40d +#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP14 0xd40e +#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP0 0xd480 +#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP2 0xd482 +#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP3 0xd483 +#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP4 0xd484 +#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP5 0xd485 +#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP6 0xd486 +#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP7 0xd487 +#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP13 0xd48d +#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP14 0xd48e +#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP0 0xd800 +#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP2 0xd802 +#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP3 0xd803 +#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP4 0xd804 +#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP5 0xd805 +#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP6 0xd806 +#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP7 0xd807 +#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP13 0xd80d +#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP14 0xd80e +#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP0 0xd880 +#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP2 0xd882 +#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP3 0xd883 +#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP4 0xd884 +#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP5 0xd885 +#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP6 0xd886 +#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP13 0xd88d +#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP14 0xd88e +#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP0 0xd900 +#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP2 0xd902 +#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP3 0xd903 +#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP4 0xd904 +#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP5 0xd905 +#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP6 0xd906 +#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP13 0xd90d +#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP14 0xd90e +#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define regHARD_RST_CTRL 0xe000 +#define regHARD_RST_CTRL_BASE_IDX 8 +#define regSELF_SOFT_RST 0xe002 +#define regSELF_SOFT_RST_BASE_IDX 8 +#define regBIF_GFX_DRV_VPU_RST 0xe003 +#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL 0xe004 +#define regBIF_RST_MISC_CTRL_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL2 0xe005 +#define regBIF_RST_MISC_CTRL2_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL3 0xe006 +#define regBIF_RST_MISC_CTRL3_BASE_IDX 8 +#define regDEV0_PF0_FLR_RST_CTRL 0xe008 +#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 8 +#define regDEV0_PF1_FLR_RST_CTRL 0xe009 +#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 8 +#define regBIF_INST_RESET_INTR_STS 0xe010 +#define regBIF_INST_RESET_INTR_STS_BASE_IDX 8 +#define regBIF_PF_FLR_INTR_STS 0xe011 +#define regBIF_PF_FLR_INTR_STS_BASE_IDX 8 +#define regBIF_D3HOTD0_INTR_STS 0xe012 +#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 8 +#define regBIF_POWER_INTR_STS 0xe014 +#define regBIF_POWER_INTR_STS_BASE_IDX 8 +#define regBIF_PF_DSTATE_INTR_STS 0xe015 +#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 8 +#define regSELF_SOFT_RST_2 0xe016 +#define regSELF_SOFT_RST_2_BASE_IDX 8 +#define regBIF_INST_RESET_INTR_MASK 0xe020 +#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_FLR_INTR_MASK 0xe021 +#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 8 +#define regBIF_D3HOTD0_INTR_MASK 0xe022 +#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 8 +#define regBIF_POWER_INTR_MASK 0xe024 +#define regBIF_POWER_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_DSTATE_INTR_MASK 0xe025 +#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_FLR_RST 0xe040 +#define regBIF_PF_FLR_RST_BASE_IDX 8 +#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 +#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 8 +#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 +#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 8 +#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 +#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 8 +#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 +#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 8 +#define regBIF_PORT0_DSTATE_VALUE 0xe230 +#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define regREGS_ROM_OFFSET_CTRL 0xcc23 +#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 8 +#define regNBIF_STRAP_BIOS_CNTL 0xcc81 +#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_0 0xcd00 +#define regDOORBELL0_CTRL_ENTRY_0_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_1 0xcd01 +#define regDOORBELL0_CTRL_ENTRY_1_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_2 0xcd02 +#define regDOORBELL0_CTRL_ENTRY_2_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_3 0xcd03 +#define regDOORBELL0_CTRL_ENTRY_3_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_4 0xcd04 +#define regDOORBELL0_CTRL_ENTRY_4_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_5 0xcd05 +#define regDOORBELL0_CTRL_ENTRY_5_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_6 0xcd06 +#define regDOORBELL0_CTRL_ENTRY_6_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_7 0xcd07 +#define regDOORBELL0_CTRL_ENTRY_7_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_8 0xcd08 +#define regDOORBELL0_CTRL_ENTRY_8_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_9 0xcd09 +#define regDOORBELL0_CTRL_ENTRY_9_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_10 0xcd0a +#define regDOORBELL0_CTRL_ENTRY_10_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_11 0xcd0b +#define regDOORBELL0_CTRL_ENTRY_11_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_12 0xcd0c +#define regDOORBELL0_CTRL_ENTRY_12_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_13 0xcd0d +#define regDOORBELL0_CTRL_ENTRY_13_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_14 0xcd0e +#define regDOORBELL0_CTRL_ENTRY_14_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_15 0xcd0f +#define regDOORBELL0_CTRL_ENTRY_15_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_16 0xcd10 +#define regDOORBELL0_CTRL_ENTRY_16_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_17 0xcd11 +#define regDOORBELL0_CTRL_ENTRY_17_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_18 0xcd12 +#define regDOORBELL0_CTRL_ENTRY_18_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_19 0xcd13 +#define regDOORBELL0_CTRL_ENTRY_19_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_20 0xcd14 +#define regDOORBELL0_CTRL_ENTRY_20_BASE_IDX 8 +#define regAID0_VF0_BASE_ADDR 0xcd40 +#define regAID0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF0_BASE_ADDR 0xcd41 +#define regAID1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF0_BASE_ADDR 0xcd42 +#define regAID2_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF0_BASE_ADDR 0xcd43 +#define regAID3_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF0_BASE_ADDR 0xcd44 +#define regAID0_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF0_BASE_ADDR 0xcd45 +#define regAID0_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF0_BASE_ADDR 0xcd46 +#define regAID1_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF0_BASE_ADDR 0xcd47 +#define regAID1_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF0_BASE_ADDR 0xcd48 +#define regAID2_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF0_BASE_ADDR 0xcd49 +#define regAID2_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF0_BASE_ADDR 0xcd4a +#define regAID3_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF0_BASE_ADDR 0xcd4b +#define regAID3_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF0_BASE_ADDR 0xcd4c +#define regAID0_NBIF_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF0_BASE_ADDR 0xcd4d +#define regAID0_ATHUB_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF0_BASE_ADDR 0xcd4e +#define regAID0_IH_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF0_BASE_ADDR 0xcd4f +#define regAID0_HDP_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF1_BASE_ADDR 0xcd50 +#define regAID0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF1_BASE_ADDR 0xcd51 +#define regAID1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF1_BASE_ADDR 0xcd52 +#define regAID2_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF1_BASE_ADDR 0xcd53 +#define regAID3_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF1_BASE_ADDR 0xcd54 +#define regAID0_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF1_BASE_ADDR 0xcd55 +#define regAID0_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF1_BASE_ADDR 0xcd56 +#define regAID1_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF1_BASE_ADDR 0xcd57 +#define regAID1_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF1_BASE_ADDR 0xcd58 +#define regAID2_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF1_BASE_ADDR 0xcd59 +#define regAID2_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF1_BASE_ADDR 0xcd5a +#define regAID3_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF1_BASE_ADDR 0xcd5b +#define regAID3_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF1_BASE_ADDR 0xcd5c +#define regAID0_NBIF_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF1_BASE_ADDR 0xcd5d +#define regAID0_ATHUB_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF1_BASE_ADDR 0xcd5e +#define regAID0_IH_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF1_BASE_ADDR 0xcd5f +#define regAID0_HDP_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF2_BASE_ADDR 0xcd60 +#define regAID0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF2_BASE_ADDR 0xcd61 +#define regAID1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF2_BASE_ADDR 0xcd62 +#define regAID2_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF2_BASE_ADDR 0xcd63 +#define regAID3_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF2_BASE_ADDR 0xcd64 +#define regAID0_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF2_BASE_ADDR 0xcd65 +#define regAID0_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF2_BASE_ADDR 0xcd66 +#define regAID1_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF2_BASE_ADDR 0xcd67 +#define regAID1_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF2_BASE_ADDR 0xcd68 +#define regAID2_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF2_BASE_ADDR 0xcd69 +#define regAID2_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF2_BASE_ADDR 0xcd6a +#define regAID3_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF2_BASE_ADDR 0xcd6b +#define regAID3_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF2_BASE_ADDR 0xcd6c +#define regAID0_NBIF_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF2_BASE_ADDR 0xcd6d +#define regAID0_ATHUB_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF2_BASE_ADDR 0xcd6e +#define regAID0_IH_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF2_BASE_ADDR 0xcd6f +#define regAID0_HDP_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF3_BASE_ADDR 0xcd70 +#define regAID0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF3_BASE_ADDR 0xcd71 +#define regAID1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF3_BASE_ADDR 0xcd72 +#define regAID2_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF3_BASE_ADDR 0xcd73 +#define regAID3_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF3_BASE_ADDR 0xcd74 +#define regAID0_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF3_BASE_ADDR 0xcd75 +#define regAID0_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF3_BASE_ADDR 0xcd76 +#define regAID1_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF3_BASE_ADDR 0xcd77 +#define regAID1_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF3_BASE_ADDR 0xcd78 +#define regAID2_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF3_BASE_ADDR 0xcd79 +#define regAID2_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF3_BASE_ADDR 0xcd7a +#define regAID3_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF3_BASE_ADDR 0xcd7b +#define regAID3_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF3_BASE_ADDR 0xcd7c +#define regAID0_NBIF_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF3_BASE_ADDR 0xcd7d +#define regAID0_ATHUB_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF3_BASE_ADDR 0xcd7e +#define regAID0_IH_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF3_BASE_ADDR 0xcd7f +#define regAID0_HDP_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF4_BASE_ADDR 0xcd80 +#define regAID0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF4_BASE_ADDR 0xcd81 +#define regAID1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF4_BASE_ADDR 0xcd82 +#define regAID2_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF4_BASE_ADDR 0xcd83 +#define regAID3_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF4_BASE_ADDR 0xcd84 +#define regAID0_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF4_BASE_ADDR 0xcd85 +#define regAID0_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF4_BASE_ADDR 0xcd86 +#define regAID1_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF4_BASE_ADDR 0xcd87 +#define regAID1_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF4_BASE_ADDR 0xcd88 +#define regAID2_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF4_BASE_ADDR 0xcd89 +#define regAID2_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF4_BASE_ADDR 0xcd8a +#define regAID3_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF4_BASE_ADDR 0xcd8b +#define regAID3_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF4_BASE_ADDR 0xcd8c +#define regAID0_NBIF_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF4_BASE_ADDR 0xcd8d +#define regAID0_ATHUB_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF4_BASE_ADDR 0xcd8e +#define regAID0_IH_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF4_BASE_ADDR 0xcd8f +#define regAID0_HDP_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF5_BASE_ADDR 0xcd90 +#define regAID0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF5_BASE_ADDR 0xcd91 +#define regAID1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF5_BASE_ADDR 0xcd92 +#define regAID2_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF5_BASE_ADDR 0xcd93 +#define regAID3_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF5_BASE_ADDR 0xcd94 +#define regAID0_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF5_BASE_ADDR 0xcd95 +#define regAID0_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF5_BASE_ADDR 0xcd96 +#define regAID1_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF5_BASE_ADDR 0xcd97 +#define regAID1_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF5_BASE_ADDR 0xcd98 +#define regAID2_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF5_BASE_ADDR 0xcd99 +#define regAID2_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF5_BASE_ADDR 0xcd9a +#define regAID3_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF5_BASE_ADDR 0xcd9b +#define regAID3_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF5_BASE_ADDR 0xcd9c +#define regAID0_NBIF_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF5_BASE_ADDR 0xcd9d +#define regAID0_ATHUB_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF5_BASE_ADDR 0xcd9e +#define regAID0_IH_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF5_BASE_ADDR 0xcd9f +#define regAID0_HDP_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF6_BASE_ADDR 0xcda0 +#define regAID0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF6_BASE_ADDR 0xcda1 +#define regAID1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF6_BASE_ADDR 0xcda2 +#define regAID2_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF6_BASE_ADDR 0xcda3 +#define regAID3_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF6_BASE_ADDR 0xcda4 +#define regAID0_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF6_BASE_ADDR 0xcda5 +#define regAID0_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF6_BASE_ADDR 0xcda6 +#define regAID1_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF6_BASE_ADDR 0xcda7 +#define regAID1_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF6_BASE_ADDR 0xcda8 +#define regAID2_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF6_BASE_ADDR 0xcda9 +#define regAID2_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF6_BASE_ADDR 0xcdaa +#define regAID3_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF6_BASE_ADDR 0xcdab +#define regAID3_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF6_BASE_ADDR 0xcdac +#define regAID0_NBIF_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF6_BASE_ADDR 0xcdad +#define regAID0_ATHUB_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF6_BASE_ADDR 0xcdae +#define regAID0_IH_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF6_BASE_ADDR 0xcdaf +#define regAID0_HDP_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF7_BASE_ADDR 0xcdb0 +#define regAID0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF7_BASE_ADDR 0xcdb1 +#define regAID1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF7_BASE_ADDR 0xcdb2 +#define regAID2_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF7_BASE_ADDR 0xcdb3 +#define regAID3_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF7_BASE_ADDR 0xcdb4 +#define regAID0_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF7_BASE_ADDR 0xcdb5 +#define regAID0_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF7_BASE_ADDR 0xcdb6 +#define regAID1_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF7_BASE_ADDR 0xcdb7 +#define regAID1_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF7_BASE_ADDR 0xcdb8 +#define regAID2_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF7_BASE_ADDR 0xcdb9 +#define regAID2_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF7_BASE_ADDR 0xcdba +#define regAID3_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF7_BASE_ADDR 0xcdbb +#define regAID3_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF7_BASE_ADDR 0xcdbc +#define regAID0_NBIF_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF7_BASE_ADDR 0xcdbd +#define regAID0_ATHUB_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF7_BASE_ADDR 0xcdbe +#define regAID0_IH_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF7_BASE_ADDR 0xcdbf +#define regAID0_HDP_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_PF_BASE_ADDR 0xcdc0 +#define regAID0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_PF_BASE_ADDR 0xcdc1 +#define regAID0_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_PF_BASE_ADDR 0xcdc2 +#define regAID0_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_PF_BASE_ADDR 0xcdc3 +#define regAID1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_PF_BASE_ADDR 0xcdc4 +#define regAID1_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_PF_BASE_ADDR 0xcdc5 +#define regAID1_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_PF_BASE_ADDR 0xcdc6 +#define regAID2_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_PF_BASE_ADDR 0xcdc7 +#define regAID2_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_PF_BASE_ADDR 0xcdc8 +#define regAID2_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_PF_BASE_ADDR 0xcdc9 +#define regAID3_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_PF_BASE_ADDR 0xcdca +#define regAID3_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_PF_BASE_ADDR 0xcdcb +#define regAID3_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regNBIF_RRMT_CNTL 0xcddc +#define regNBIF_RRMT_CNTL_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_PF 0xcf6e +#define regBIFC_DOORBELL_ACCESS_EN_PF_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF0 0xcf6f +#define regBIFC_DOORBELL_ACCESS_EN_VF0_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF1 0xcf70 +#define regBIFC_DOORBELL_ACCESS_EN_VF1_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF2 0xcf71 +#define regBIFC_DOORBELL_ACCESS_EN_VF2_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF3 0xcf72 +#define regBIFC_DOORBELL_ACCESS_EN_VF3_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF4 0xcf73 +#define regBIFC_DOORBELL_ACCESS_EN_VF4_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF5 0xcf74 +#define regBIFC_DOORBELL_ACCESS_EN_VF5_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF6 0xcf75 +#define regBIFC_DOORBELL_ACCESS_EN_VF6_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF7 0xcf76 +#define regBIFC_DOORBELL_ACCESS_EN_VF7_BASE_IDX 8 +#define regMISC_SCRATCH 0xe800 +#define regMISC_SCRATCH_BASE_IDX 8 +#define regINTR_LINE_POLARITY 0xe801 +#define regINTR_LINE_POLARITY_BASE_IDX 8 +#define regINTR_LINE_ENABLE 0xe802 +#define regINTR_LINE_ENABLE_BASE_IDX 8 +#define regOUTSTANDING_VC_ALLOC 0xe803 +#define regOUTSTANDING_VC_ALLOC_BASE_IDX 8 +#define regBIFC_MISC_CTRL0 0xe804 +#define regBIFC_MISC_CTRL0_BASE_IDX 8 +#define regBIFC_MISC_CTRL1 0xe805 +#define regBIFC_MISC_CTRL1_BASE_IDX 8 +#define regBIFC_BME_ERR_LOG_LB 0xe806 +#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 8 +#define regBIFC_LC_TIMER_CTRL 0xe807 +#define regBIFC_LC_TIMER_CTRL_BASE_IDX 8 +#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 +#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 8 +#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a +#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 8 +#define regBME_DUMMY_CNTL_0 0xe825 +#define regBME_DUMMY_CNTL_0_BASE_IDX 8 +#define regBIFC_THT_CNTL 0xe827 +#define regBIFC_THT_CNTL_BASE_IDX 8 +#define regBIFC_HSTARB_CNTL 0xe828 +#define regBIFC_HSTARB_CNTL_BASE_IDX 8 +#define regBIFC_GSI_CNTL 0xe829 +#define regBIFC_GSI_CNTL_BASE_IDX 8 +#define regBIFC_PCIEFUNC_CNTL 0xe82a +#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 8 +#define regBIFC_PASID_CHECK_DIS 0xe82b +#define regBIFC_PASID_CHECK_DIS_BASE_IDX 8 +#define regBIFC_SDP_CNTL_0 0xe82c +#define regBIFC_SDP_CNTL_0_BASE_IDX 8 +#define regBIFC_SDP_CNTL_1 0xe82d +#define regBIFC_SDP_CNTL_1_BASE_IDX 8 +#define regBIFC_PASID_STS 0xe82e +#define regBIFC_PASID_STS_BASE_IDX 8 +#define regBIFC_ATHUB_ACT_CNTL 0xe82f +#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 8 +#define regBIFC_PERF_CNTL_0 0xe830 +#define regBIFC_PERF_CNTL_0_BASE_IDX 8 +#define regBIFC_PERF_CNTL_1 0xe831 +#define regBIFC_PERF_CNTL_1_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 8 +#define regNBIF_REGIF_ERRSET_CTRL 0xe836 +#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 8 +#define regBIFC_SDP_CNTL_2 0xe837 +#define regBIFC_SDP_CNTL_2_BASE_IDX 8 +#define regNBIF_PGMST_CTRL 0xe838 +#define regNBIF_PGMST_CTRL_BASE_IDX 8 +#define regNBIF_PGSLV_CTRL 0xe839 +#define regNBIF_PGSLV_CTRL_BASE_IDX 8 +#define regNBIF_PG_MISC_CTRL 0xe83a +#define regNBIF_PG_MISC_CTRL_BASE_IDX 8 +#define regSMN_MST_EP_CNTL3 0xe83c +#define regSMN_MST_EP_CNTL3_BASE_IDX 8 +#define regSMN_MST_EP_CNTL4 0xe83d +#define regSMN_MST_EP_CNTL4_BASE_IDX 8 +#define regSMN_MST_CNTL1 0xe83e +#define regSMN_MST_CNTL1_BASE_IDX 8 +#define regSMN_MST_EP_CNTL5 0xe83f +#define regSMN_MST_EP_CNTL5_BASE_IDX 8 +#define regBIF_SELFRING_BUFFER_VID 0xe840 +#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 8 +#define regBIF_SELFRING_VECTOR_CNTL 0xe841 +#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 8 +#define regNBIF_STRAP_WRITE_CTRL 0xe845 +#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 8 +#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 +#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 8 +#define regNBIF_PENDING_MISC_CNTL 0xe847 +#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT 0xe848 +#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT2 0xe849 +#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT3 0xe84a +#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 8 +#define regNBIF_PWRBRK_REQUEST 0xe84c +#define regNBIF_PWRBRK_REQUEST_BASE_IDX 8 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 8 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 8 +#define regBIF_DMA_MP4_ERR_LOG 0xe870 +#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 8 +#define regBIF_PASID_ERR_LOG 0xe871 +#define regBIF_PASID_ERR_LOG_BASE_IDX 8 +#define regBIF_PASID_ERR_CLR 0xe872 +#define regBIF_PASID_ERR_CLR_BASE_IDX 8 +#define regNBIF_VWIRE_CTRL 0xe880 +#define regNBIF_VWIRE_CTRL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 +#define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 8 +#define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 +#define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 8 +#define regNBIF_MGCG_CTRL_LCLK 0xe887 +#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 8 +#define regNBIF_DS_CTRL_LCLK 0xe888 +#define regNBIF_DS_CTRL_LCLK_BASE_IDX 8 +#define regSMN_MST_CNTL0 0xe889 +#define regSMN_MST_CNTL0_BASE_IDX 8 +#define regSMN_MST_EP_CNTL1 0xe88a +#define regSMN_MST_EP_CNTL1_BASE_IDX 8 +#define regSMN_MST_EP_CNTL2 0xe88b +#define regSMN_MST_EP_CNTL2_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f +#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CTRL 0xe898 +#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 +#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a +#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 8 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c +#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d +#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 8 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 8 +#define regBIFC_BME_ERR_LOG_HB 0xe8ab +#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 8 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 8 +#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 +#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 8 +#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 +#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 8 +#define regBIFC_A2S_SDP_PORT_CTRL 0xeb00 +#define regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX 8 +#define regBIFC_A2S_CNTL_SW0 0xeb01 +#define regBIFC_A2S_CNTL_SW0_BASE_IDX 8 +#define regBIFC_A2S_MISC_CNTL 0xeb02 +#define regBIFC_A2S_MISC_CNTL_BASE_IDX 8 +#define regBIFC_A2S_TAG_ALLOC_0 0xeb03 +#define regBIFC_A2S_TAG_ALLOC_0_BASE_IDX 8 +#define regBIFC_A2S_TAG_ALLOC_1 0xeb04 +#define regBIFC_A2S_TAG_ALLOC_1_BASE_IDX 8 +#define regBIFC_A2S_CNTL_CL0 0xeb05 +#define regBIFC_A2S_CNTL_CL0_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 +#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac +#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 +#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 +#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea +#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +// base address: 0x10120000 +#define regBIF_BX1_PCIE_INDEX 0x800c +#define regBIF_BX1_PCIE_INDEX_BASE_IDX 8 +#define regBIF_BX1_PCIE_DATA 0x800d +#define regBIF_BX1_PCIE_DATA_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX2 0x800e +#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 8 +#define regBIF_BX1_PCIE_DATA2 0x800f +#define regBIF_BX1_PCIE_DATA2_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX_HI 0x8010 +#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX2_HI 0x8011 +#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 +#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 +#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a +#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b +#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_0 0x804c +#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_1 0x804d +#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_2 0x804e +#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_3 0x804f +#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_4 0x8050 +#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_5 0x8051 +#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_6 0x8052 +#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_7 0x8053 +#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_8 0x8054 +#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_9 0x8055 +#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_10 0x8056 +#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_11 0x8057 +#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_12 0x8058 +#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_13 0x8059 +#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_14 0x805a +#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_15 0x805b +#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 +#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 +#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 +#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 +#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 +#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 +#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 +#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 +#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 +#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a +#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b +#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c +#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d +#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e +#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f +#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 +#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 +#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 +#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 +#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_0 0x80a4 +#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_1 0x80a5 +#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_2 0x80a6 +#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_3 0x80a7 +#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_4 0x80a8 +#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_5 0x80a9 +#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_6 0x80aa +#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_7 0x80ab +#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_8 0x80ac +#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_9 0x80ad +#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_10 0x80ae +#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_11 0x80af +#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_12 0x80b0 +#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_13 0x80b1 +#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_14 0x80b2 +#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_15 0x80b3 +#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 +#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 +#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 +#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 +#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 +#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 +#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba +#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb +#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc +#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd +#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be +#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf +#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_PF1_MM_INDEX 0x8000 +#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 8 +#define regBIF_BX_PF1_MM_DATA 0x8001 +#define regBIF_BX_PF1_MM_DATA_BASE_IDX 8 +#define regBIF_BX_PF1_MM_INDEX_HI 0x8006 +#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x10120000 +#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 +#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 8 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 8 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BUS_CNTL 0x8e07 +#define regBIF_BX1_BUS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_SCRATCH0 0x8e08 +#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 8 +#define regBIF_BX1_BIF_SCRATCH1 0x8e09 +#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 8 +#define regBIF_BX1_BX_RESET_EN 0x8e0d +#define regBIF_BX1_BX_RESET_EN_BASE_IDX 8 +#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e +#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BX_RESET_CNTL 0x8e10 +#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 8 +#define regBIF_BX1_INTERRUPT_CNTL 0x8e11 +#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 8 +#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 +#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 8 +#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 +#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 8 +#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d +#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_FB_EN 0x8e20 +#define regBIF_BX1_BIF_FB_EN_BASE_IDX 8 +#define regBIF_BX1_BIF_INTR_CNTL 0x8e21 +#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 8 +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 8 +#define regBIF_BX1_BACO_CNTL 0x8e2b +#define regBIF_BX1_BACO_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c +#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 8 +#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 +#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 8 +#define regBIF_BX1_VF_REGWR_EN 0x8e44 +#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 8 +#define regBIF_BX1_VF_DOORBELL_EN 0x8e45 +#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 8 +#define regBIF_BX1_VF_FB_EN 0x8e46 +#define regBIF_BX1_VF_FB_EN_BASE_IDX 8 +#define regBIF_BX1_VF_REGWR_STATUS 0x8e47 +#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 8 +#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 +#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 8 +#define regBIF_BX1_VF_FB_STATUS 0x8e49 +#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 8 +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_CNTL 0x8e4f +#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_BASE 0x8e50 +#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_RPTR 0x8e51 +#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR 0x8e52 +#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 8 +#define regBIF_BX1_MAILBOX_INDEX 0x8e55 +#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 8 +#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 +#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 8 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e66 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e67 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e68 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e69 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6a +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e6b +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 8 +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e6c +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 8 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 8 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1:1 +// base address: 0x10120000 +#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 +#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 +#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 +#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 +#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 +#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 +#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 +#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d44 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d45 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d46 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d52 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d53 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d54 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d55 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d56 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d57 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d58 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d59 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d5a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5b +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5c +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5d +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_gdc_hst_sion_SIONDEC +// base address: 0x1400000 +#define regS2A_DOORBELL_ENTRY_0_CTRL 0x7a80 +#define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_1_CTRL 0x7a81 +#define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_2_CTRL 0x7a82 +#define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_3_CTRL 0x7a83 +#define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_4_CTRL 0x7a84 +#define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_5_CTRL 0x7a85 +#define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_6_CTRL 0x7a86 +#define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_7_CTRL 0x7a87 +#define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_8_CTRL 0x7a88 +#define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_9_CTRL 0x7a89 +#define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_10_CTRL 0x7a8a +#define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_11_CTRL 0x7a8b +#define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_12_CTRL 0x7a8c +#define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_13_CTRL 0x7a8d +#define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_14_CTRL 0x7a8e +#define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_15_CTRL 0x7a8f +#define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_COMMON_CTRL_REG 0x7a90 +#define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +// base address: 0x1400000 +#define regGDC1_A2S_CNTL_CL0 0x0ea0 +#define regGDC1_A2S_CNTL_CL0_BASE_IDX 5 +#define regGDC1_A2S_CNTL_CL1 0x0ea1 +#define regGDC1_A2S_CNTL_CL1_BASE_IDX 5 +#define regGDC1_A2S_CNTL3_CL0 0x0eb8 +#define regGDC1_A2S_CNTL3_CL0_BASE_IDX 5 +#define regGDC1_A2S_CNTL3_CL1 0x0eb9 +#define regGDC1_A2S_CNTL3_CL1_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW0 0x0ed0 +#define regGDC1_A2S_CNTL_SW0_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW1 0x0ed1 +#define regGDC1_A2S_CNTL_SW1_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW2 0x0ed2 +#define regGDC1_A2S_CNTL_SW2_BASE_IDX 5 +#define regGDC1_A2S_TAG_ALLOC_0 0x0edd +#define regGDC1_A2S_TAG_ALLOC_0_BASE_IDX 5 +#define regGDC1_A2S_TAG_ALLOC_1 0x0ede +#define regGDC1_A2S_TAG_ALLOC_1_BASE_IDX 5 +#define regGDC1_A2S_MISC_CNTL 0x0ee1 +#define regGDC1_A2S_MISC_CNTL_BASE_IDX 5 +#define regGDC1_SHUB_REGS_IF_CTL 0x0ee3 +#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 5 +#define regGDC1_NGDC_MGCG_CTRL 0x0eea +#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_RESERVED_0 0x0eeb +#define regGDC1_NGDC_RESERVED_0_BASE_IDX 5 +#define regGDC1_NGDC_RESERVED_1 0x0eec +#define regGDC1_NGDC_RESERVED_1_BASE_IDX 5 +#define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x0eef +#define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 5 +#define regGDC1_ATDMA_MISC_CNTL 0x0efd +#define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 5 +#define regGDC1_S2A_MISC_CNTL 0x0eff +#define regGDC1_S2A_MISC_CNTL_BASE_IDX 5 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x0f01 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PG_MISC_CTRL 0x0f18 +#define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PGMST_CTRL 0x0f19 +#define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PGSLV_CTRL 0x0f1a +#define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_sec_GDCSEC_DEC +// base address: 0x1400000 +#define regXCC_DOORBELL_FENCE 0x740c +#define regXCC_DOORBELL_FENCE_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define regSHUB_PF_FLR_RST 0x7c00 +#define regSHUB_PF_FLR_RST_BASE_IDX 5 +#define regSHUB_GFX_DRV_VPU_RST 0x7c01 +#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 5 +#define regSHUB_LINK_RESET 0x7c02 +#define regSHUB_LINK_RESET_BASE_IDX 5 +#define regSHUB_HARD_RST_CTRL 0x7c10 +#define regSHUB_HARD_RST_CTRL_BASE_IDX 5 +#define regSHUB_SOFT_RST_CTRL 0x7c11 +#define regSHUB_SOFT_RST_CTRL_BASE_IDX 5 +#define regSHUB_SDP_PORT_RST 0x7c12 +#define regSHUB_SDP_PORT_RST_BASE_IDX 5 +#define regSHUB_RST_MISC_TRL 0x7c13 +#define regSHUB_RST_MISC_TRL_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_syshub_mmreg_syshubdirect +// base address: 0x1400000 +#define regHST_CLK0_SW0_CL0_CNTL 0x4140 +#define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL0_CNTL 0x4160 +#define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL1_CNTL 0x4161 +#define regHST_CLK0_SW1_CL1_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL2_CNTL 0x4162 +#define regHST_CLK0_SW1_CL2_CNTL_BASE_IDX 5 +#define regDMA_CLK0_SW0_CL0_CNTL 0x4240 +#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 5 +#define regDMA_CLK0_SW0_CL1_CNTL 0x4241 +#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 5 +#define regNIC400_1_ASIB_0_FN_MOD 0xc042 +#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_1_IB_0_FN_MOD 0xfc42 +#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_0_FN_MOD 0x10c42 +#define regNIC400_2_ASIB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_0_QOS_CNTL 0x10c43 +#define regNIC400_2_ASIB_0_QOS_CNTL_BASE_IDX 5 +#define regNIC400_2_ASIB_0_MAX_OT 0x10c44 +#define regNIC400_2_ASIB_0_MAX_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_0_MAX_COMB_OT 0x10c45 +#define regNIC400_2_ASIB_0_MAX_COMB_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_P 0x10c46 +#define regNIC400_2_ASIB_0_AW_P_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_B 0x10c47 +#define regNIC400_2_ASIB_0_AW_B_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_R 0x10c48 +#define regNIC400_2_ASIB_0_AW_R_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_P 0x10c49 +#define regNIC400_2_ASIB_0_AR_P_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_B 0x10c4a +#define regNIC400_2_ASIB_0_AR_B_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_R 0x10c4b +#define regNIC400_2_ASIB_0_AR_R_BASE_IDX 5 +#define regNIC400_2_ASIB_0_TARGET_FC 0x10c4c +#define regNIC400_2_ASIB_0_TARGET_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_0_KI_FC 0x10c4d +#define regNIC400_2_ASIB_0_KI_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_0_QOS_RANGE 0x10c4e +#define regNIC400_2_ASIB_0_QOS_RANGE_BASE_IDX 5 +#define regNIC400_2_ASIB_1_FN_MOD 0x11042 +#define regNIC400_2_ASIB_1_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_1_QOS_CNTL 0x11043 +#define regNIC400_2_ASIB_1_QOS_CNTL_BASE_IDX 5 +#define regNIC400_2_ASIB_1_MAX_OT 0x11044 +#define regNIC400_2_ASIB_1_MAX_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_1_MAX_COMB_OT 0x11045 +#define regNIC400_2_ASIB_1_MAX_COMB_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_P 0x11046 +#define regNIC400_2_ASIB_1_AW_P_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_B 0x11047 +#define regNIC400_2_ASIB_1_AW_B_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_R 0x11048 +#define regNIC400_2_ASIB_1_AW_R_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_P 0x11049 +#define regNIC400_2_ASIB_1_AR_P_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_B 0x1104a +#define regNIC400_2_ASIB_1_AR_B_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_R 0x1104b +#define regNIC400_2_ASIB_1_AR_R_BASE_IDX 5 +#define regNIC400_2_ASIB_1_TARGET_FC 0x1104c +#define regNIC400_2_ASIB_1_TARGET_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_1_KI_FC 0x1104d +#define regNIC400_2_ASIB_1_KI_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_1_QOS_RANGE 0x1104e +#define regNIC400_2_ASIB_1_QOS_RANGE_BASE_IDX 5 +#define regNIC400_2_IB_0_FN_MOD 0x13c42 +#define regNIC400_2_IB_0_FN_MOD_BASE_IDX 5 + + +// addressBlock: aid_nbio_iohub_nb_nbcfg_nb_cfgdec +// base address: 0x13b00000 +#define regNB_NBCFG0_NBCFG_SCRATCH_4 0xe8001e +#define regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_misc_misc_cfgdec +// base address: 0x13b10000 +#define regNB_CNTL 0xe84000 +#define regNB_CNTL_BASE_IDX 8 +#define regNB_SPARE1 0xe84003 +#define regNB_SPARE1_BASE_IDX 8 +#define regNB_SPARE2 0xe84004 +#define regNB_SPARE2_BASE_IDX 8 +#define regNB_REVID 0xe84005 +#define regNB_REVID_BASE_IDX 8 +#define regNBIO_LCLK_DS_MASK 0xe84009 +#define regNBIO_LCLK_DS_MASK_BASE_IDX 8 +#define regNB_BUS_NUM_CNTL 0xe84011 +#define regNB_BUS_NUM_CNTL_BASE_IDX 8 +#define regNB_MMIOBASE 0xe84017 +#define regNB_MMIOBASE_BASE_IDX 8 +#define regNB_MMIOLIMIT 0xe84018 +#define regNB_MMIOLIMIT_BASE_IDX 8 +#define regNB_LOWER_TOP_OF_DRAM2 0xe84019 +#define regNB_LOWER_TOP_OF_DRAM2_BASE_IDX 8 +#define regNB_UPPER_TOP_OF_DRAM2 0xe8401a +#define regNB_UPPER_TOP_OF_DRAM2_BASE_IDX 8 +#define regNB_LOWER_DRAM2_BASE 0xe8401b +#define regNB_LOWER_DRAM2_BASE_BASE_IDX 8 +#define regNB_UPPER_DRAM2_BASE 0xe8401c +#define regNB_UPPER_DRAM2_BASE_BASE_IDX 8 +#define regSB_LOCATION 0xe8401f +#define regSB_LOCATION_BASE_IDX 8 +#define regSW_US_LOCATION 0xe84020 +#define regSW_US_LOCATION_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr0 0xe8402e +#define regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr1 0xe8402f +#define regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr2 0xe84030 +#define regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr3 0xe84031 +#define regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr4 0xe84032 +#define regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr5 0xe84033 +#define regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr6 0xe84034 +#define regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr7 0xe84035 +#define regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr8 0xe84036 +#define regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr10 0xe84038 +#define regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr11 0xe84039 +#define regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr12 0xe8403a +#define regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr13 0xe8403b +#define regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX 8 +#define regSW_NMI_CNTL 0xe84042 +#define regSW_NMI_CNTL_BASE_IDX 8 +#define regSW_SMI_CNTL 0xe84043 +#define regSW_SMI_CNTL_BASE_IDX 8 +#define regSW_SCI_CNTL 0xe84044 +#define regSW_SCI_CNTL_BASE_IDX 8 +#define regAPML_SW_STATUS 0xe84045 +#define regAPML_SW_STATUS_BASE_IDX 8 +#define regSW_GIC_SPI_CNTL 0xe84047 +#define regSW_GIC_SPI_CNTL_BASE_IDX 8 +#define regSW_SYNCFLOOD_CNTL 0xe84049 +#define regSW_SYNCFLOOD_CNTL_BASE_IDX 8 +#define regNB_TOP_OF_DRAM3 0xe8404e +#define regNB_TOP_OF_DRAM3_BASE_IDX 8 +#define regCAM_CONTROL 0xe84052 +#define regCAM_CONTROL_BASE_IDX 8 +#define regCAM_TARGET_INDEX_ADDR_BOTTOM 0xe84053 +#define regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX 8 +#define regCAM_TARGET_INDEX_ADDR_TOP 0xe84054 +#define regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX 8 +#define regCAM_TARGET_INDEX_DATA 0xe84055 +#define regCAM_TARGET_INDEX_DATA_BASE_IDX 8 +#define regCAM_TARGET_INDEX_DATA_MASK 0xe84056 +#define regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX 8 +#define regCAM_TARGET_DATA_ADDR_BOTTOM 0xe84057 +#define regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX 8 +#define regCAM_TARGET_DATA_ADDR_TOP 0xe84059 +#define regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX 8 +#define regCAM_TARGET_DATA 0xe8405a +#define regCAM_TARGET_DATA_BASE_IDX 8 +#define regCAM_TARGET_DATA_MASK 0xe8405b +#define regCAM_TARGET_DATA_MASK_BASE_IDX 8 +#define regP_DMA_DROPPED_LOG_LOWER 0xe84060 +#define regP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 +#define regP_DMA_DROPPED_LOG_UPPER 0xe84061 +#define regP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 +#define regNP_DMA_DROPPED_LOG_LOWER 0xe84062 +#define regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 +#define regNP_DMA_DROPPED_LOG_UPPER 0xe84063 +#define regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 +#define regPCIE_VDM_NODE0_CTRL4 0xe84064 +#define regPCIE_VDM_NODE0_CTRL4_BASE_IDX 8 +#define regPCIE_VDM_CNTL2 0xe8408c +#define regPCIE_VDM_CNTL2_BASE_IDX 8 +#define regPCIE_VDM_CNTL3 0xe8408d +#define regPCIE_VDM_CNTL3_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT0_0 0xe84090 +#define regSTALL_CONTROL_XBARPORT0_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT0_1 0xe84091 +#define regSTALL_CONTROL_XBARPORT0_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT1_0 0xe84093 +#define regSTALL_CONTROL_XBARPORT1_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT1_1 0xe84094 +#define regSTALL_CONTROL_XBARPORT1_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT2_0 0xe84096 +#define regSTALL_CONTROL_XBARPORT2_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT2_1 0xe84097 +#define regSTALL_CONTROL_XBARPORT2_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT3_0 0xe84099 +#define regSTALL_CONTROL_XBARPORT3_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT3_1 0xe8409a +#define regSTALL_CONTROL_XBARPORT3_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT4_0 0xe8409c +#define regSTALL_CONTROL_XBARPORT4_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT4_1 0xe8409d +#define regSTALL_CONTROL_XBARPORT4_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT5_0 0xe8409f +#define regSTALL_CONTROL_XBARPORT5_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT5_1 0xe840a0 +#define regSTALL_CONTROL_XBARPORT5_1_BASE_IDX 8 +#define regNB_DRAM3_BASE 0xe840b1 +#define regNB_DRAM3_BASE_BASE_IDX 8 +#define regPSP_BASE_ADDR_LO 0xe840b8 +#define regPSP_BASE_ADDR_LO_BASE_IDX 8 +#define regPSP_BASE_ADDR_HI 0xe840b9 +#define regPSP_BASE_ADDR_HI_BASE_IDX 8 +#define regSMU_BASE_ADDR_LO 0xe840ba +#define regSMU_BASE_ADDR_LO_BASE_IDX 8 +#define regSMU_BASE_ADDR_HI 0xe840bb +#define regSMU_BASE_ADDR_HI_BASE_IDX 8 +#define regSCRATCH_4 0xe840fc +#define regSCRATCH_4_BASE_IDX 8 +#define regSCRATCH_5 0xe840fd +#define regSCRATCH_5_BASE_IDX 8 +#define regSMU_BLOCK_CPU 0xe840fe +#define regSMU_BLOCK_CPU_BASE_IDX 8 +#define regSMU_BLOCK_CPU_STATUS 0xe840ff +#define regSMU_BLOCK_CPU_STATUS_BASE_IDX 8 +#define regTRAP_STATUS 0xe84100 +#define regTRAP_STATUS_BASE_IDX 8 +#define regTRAP_REQUEST0 0xe84101 +#define regTRAP_REQUEST0_BASE_IDX 8 +#define regTRAP_REQUEST1 0xe84102 +#define regTRAP_REQUEST1_BASE_IDX 8 +#define regTRAP_REQUEST2 0xe84103 +#define regTRAP_REQUEST2_BASE_IDX 8 +#define regTRAP_REQUEST3 0xe84104 +#define regTRAP_REQUEST3_BASE_IDX 8 +#define regTRAP_REQUEST4 0xe84105 +#define regTRAP_REQUEST4_BASE_IDX 8 +#define regTRAP_REQUEST5 0xe84106 +#define regTRAP_REQUEST5_BASE_IDX 8 +#define regTRAP_REQUEST_DATASTRB0 0xe84108 +#define regTRAP_REQUEST_DATASTRB0_BASE_IDX 8 +#define regTRAP_REQUEST_DATASTRB1 0xe84109 +#define regTRAP_REQUEST_DATASTRB1_BASE_IDX 8 +#define regTRAP_REQUEST_DATA0 0xe84110 +#define regTRAP_REQUEST_DATA0_BASE_IDX 8 +#define regTRAP_REQUEST_DATA1 0xe84111 +#define regTRAP_REQUEST_DATA1_BASE_IDX 8 +#define regTRAP_REQUEST_DATA2 0xe84112 +#define regTRAP_REQUEST_DATA2_BASE_IDX 8 +#define regTRAP_REQUEST_DATA3 0xe84113 +#define regTRAP_REQUEST_DATA3_BASE_IDX 8 +#define regTRAP_REQUEST_DATA4 0xe84114 +#define regTRAP_REQUEST_DATA4_BASE_IDX 8 +#define regTRAP_REQUEST_DATA5 0xe84115 +#define regTRAP_REQUEST_DATA5_BASE_IDX 8 +#define regTRAP_REQUEST_DATA6 0xe84116 +#define regTRAP_REQUEST_DATA6_BASE_IDX 8 +#define regTRAP_REQUEST_DATA7 0xe84117 +#define regTRAP_REQUEST_DATA7_BASE_IDX 8 +#define regTRAP_REQUEST_DATA8 0xe84118 +#define regTRAP_REQUEST_DATA8_BASE_IDX 8 +#define regTRAP_REQUEST_DATA9 0xe84119 +#define regTRAP_REQUEST_DATA9_BASE_IDX 8 +#define regTRAP_REQUEST_DATA10 0xe8411a +#define regTRAP_REQUEST_DATA10_BASE_IDX 8 +#define regTRAP_REQUEST_DATA11 0xe8411b +#define regTRAP_REQUEST_DATA11_BASE_IDX 8 +#define regTRAP_REQUEST_DATA12 0xe8411c +#define regTRAP_REQUEST_DATA12_BASE_IDX 8 +#define regTRAP_REQUEST_DATA13 0xe8411d +#define regTRAP_REQUEST_DATA13_BASE_IDX 8 +#define regTRAP_REQUEST_DATA14 0xe8411e +#define regTRAP_REQUEST_DATA14_BASE_IDX 8 +#define regTRAP_REQUEST_DATA15 0xe8411f +#define regTRAP_REQUEST_DATA15_BASE_IDX 8 +#define regTRAP_RESPONSE_CONTROL 0xe84130 +#define regTRAP_RESPONSE_CONTROL_BASE_IDX 8 +#define regTRAP_RESPONSE0 0xe84131 +#define regTRAP_RESPONSE0_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA0 0xe84140 +#define regTRAP_RESPONSE_DATA0_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA1 0xe84141 +#define regTRAP_RESPONSE_DATA1_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA2 0xe84142 +#define regTRAP_RESPONSE_DATA2_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA3 0xe84143 +#define regTRAP_RESPONSE_DATA3_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA4 0xe84144 +#define regTRAP_RESPONSE_DATA4_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA5 0xe84145 +#define regTRAP_RESPONSE_DATA5_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA6 0xe84146 +#define regTRAP_RESPONSE_DATA6_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA7 0xe84147 +#define regTRAP_RESPONSE_DATA7_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA8 0xe84148 +#define regTRAP_RESPONSE_DATA8_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA9 0xe84149 +#define regTRAP_RESPONSE_DATA9_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA10 0xe8414a +#define regTRAP_RESPONSE_DATA10_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA11 0xe8414b +#define regTRAP_RESPONSE_DATA11_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA12 0xe8414c +#define regTRAP_RESPONSE_DATA12_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA13 0xe8414d +#define regTRAP_RESPONSE_DATA13_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA14 0xe8414e +#define regTRAP_RESPONSE_DATA14_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA15 0xe8414f +#define regTRAP_RESPONSE_DATA15_BASE_IDX 8 +#define regTRAP0_CONTROL0 0xe84200 +#define regTRAP0_CONTROL0_BASE_IDX 8 +#define regTRAP0_ADDRESS_LO 0xe84202 +#define regTRAP0_ADDRESS_LO_BASE_IDX 8 +#define regTRAP0_ADDRESS_HI 0xe84203 +#define regTRAP0_ADDRESS_HI_BASE_IDX 8 +#define regTRAP0_COMMAND 0xe84204 +#define regTRAP0_COMMAND_BASE_IDX 8 +#define regTRAP0_ADDRESS_LO_MASK 0xe84206 +#define regTRAP0_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP0_ADDRESS_HI_MASK 0xe84207 +#define regTRAP0_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP0_COMMAND_MASK 0xe84208 +#define regTRAP0_COMMAND_MASK_BASE_IDX 8 +#define regTRAP1_CONTROL0 0xe84210 +#define regTRAP1_CONTROL0_BASE_IDX 8 +#define regTRAP1_ADDRESS_LO 0xe84212 +#define regTRAP1_ADDRESS_LO_BASE_IDX 8 +#define regTRAP1_ADDRESS_HI 0xe84213 +#define regTRAP1_ADDRESS_HI_BASE_IDX 8 +#define regTRAP1_COMMAND 0xe84214 +#define regTRAP1_COMMAND_BASE_IDX 8 +#define regTRAP1_ADDRESS_LO_MASK 0xe84216 +#define regTRAP1_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP1_ADDRESS_HI_MASK 0xe84217 +#define regTRAP1_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP1_COMMAND_MASK 0xe84218 +#define regTRAP1_COMMAND_MASK_BASE_IDX 8 +#define regTRAP2_CONTROL0 0xe84220 +#define regTRAP2_CONTROL0_BASE_IDX 8 +#define regTRAP2_ADDRESS_LO 0xe84222 +#define regTRAP2_ADDRESS_LO_BASE_IDX 8 +#define regTRAP2_ADDRESS_HI 0xe84223 +#define regTRAP2_ADDRESS_HI_BASE_IDX 8 +#define regTRAP2_COMMAND 0xe84224 +#define regTRAP2_COMMAND_BASE_IDX 8 +#define regTRAP2_ADDRESS_LO_MASK 0xe84226 +#define regTRAP2_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP2_ADDRESS_HI_MASK 0xe84227 +#define regTRAP2_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP2_COMMAND_MASK 0xe84228 +#define regTRAP2_COMMAND_MASK_BASE_IDX 8 +#define regTRAP3_CONTROL0 0xe84230 +#define regTRAP3_CONTROL0_BASE_IDX 8 +#define regTRAP3_ADDRESS_LO 0xe84232 +#define regTRAP3_ADDRESS_LO_BASE_IDX 8 +#define regTRAP3_ADDRESS_HI 0xe84233 +#define regTRAP3_ADDRESS_HI_BASE_IDX 8 +#define regTRAP3_COMMAND 0xe84234 +#define regTRAP3_COMMAND_BASE_IDX 8 +#define regTRAP3_ADDRESS_LO_MASK 0xe84236 +#define regTRAP3_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP3_ADDRESS_HI_MASK 0xe84237 +#define regTRAP3_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP3_COMMAND_MASK 0xe84238 +#define regTRAP3_COMMAND_MASK_BASE_IDX 8 +#define regTRAP4_CONTROL0 0xe84240 +#define regTRAP4_CONTROL0_BASE_IDX 8 +#define regTRAP4_ADDRESS_LO 0xe84242 +#define regTRAP4_ADDRESS_LO_BASE_IDX 8 +#define regTRAP4_ADDRESS_HI 0xe84243 +#define regTRAP4_ADDRESS_HI_BASE_IDX 8 +#define regTRAP4_COMMAND 0xe84244 +#define regTRAP4_COMMAND_BASE_IDX 8 +#define regTRAP4_ADDRESS_LO_MASK 0xe84246 +#define regTRAP4_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP4_ADDRESS_HI_MASK 0xe84247 +#define regTRAP4_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP4_COMMAND_MASK 0xe84248 +#define regTRAP4_COMMAND_MASK_BASE_IDX 8 +#define regTRAP5_CONTROL0 0xe84250 +#define regTRAP5_CONTROL0_BASE_IDX 8 +#define regTRAP5_ADDRESS_LO 0xe84252 +#define regTRAP5_ADDRESS_LO_BASE_IDX 8 +#define regTRAP5_ADDRESS_HI 0xe84253 +#define regTRAP5_ADDRESS_HI_BASE_IDX 8 +#define regTRAP5_COMMAND 0xe84254 +#define regTRAP5_COMMAND_BASE_IDX 8 +#define regTRAP5_ADDRESS_LO_MASK 0xe84256 +#define regTRAP5_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP5_ADDRESS_HI_MASK 0xe84257 +#define regTRAP5_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP5_COMMAND_MASK 0xe84258 +#define regTRAP5_COMMAND_MASK_BASE_IDX 8 +#define regTRAP6_CONTROL0 0xe84260 +#define regTRAP6_CONTROL0_BASE_IDX 8 +#define regTRAP6_ADDRESS_LO 0xe84262 +#define regTRAP6_ADDRESS_LO_BASE_IDX 8 +#define regTRAP6_ADDRESS_HI 0xe84263 +#define regTRAP6_ADDRESS_HI_BASE_IDX 8 +#define regTRAP6_COMMAND 0xe84264 +#define regTRAP6_COMMAND_BASE_IDX 8 +#define regTRAP6_ADDRESS_LO_MASK 0xe84266 +#define regTRAP6_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP6_ADDRESS_HI_MASK 0xe84267 +#define regTRAP6_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP6_COMMAND_MASK 0xe84268 +#define regTRAP6_COMMAND_MASK_BASE_IDX 8 +#define regTRAP7_CONTROL0 0xe84270 +#define regTRAP7_CONTROL0_BASE_IDX 8 +#define regTRAP7_ADDRESS_LO 0xe84272 +#define regTRAP7_ADDRESS_LO_BASE_IDX 8 +#define regTRAP7_ADDRESS_HI 0xe84273 +#define regTRAP7_ADDRESS_HI_BASE_IDX 8 +#define regTRAP7_COMMAND 0xe84274 +#define regTRAP7_COMMAND_BASE_IDX 8 +#define regTRAP7_ADDRESS_LO_MASK 0xe84276 +#define regTRAP7_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP7_ADDRESS_HI_MASK 0xe84277 +#define regTRAP7_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP7_COMMAND_MASK 0xe84278 +#define regTRAP7_COMMAND_MASK_BASE_IDX 8 +#define regTRAP8_CONTROL0 0xe84280 +#define regTRAP8_CONTROL0_BASE_IDX 8 +#define regTRAP8_ADDRESS_LO 0xe84282 +#define regTRAP8_ADDRESS_LO_BASE_IDX 8 +#define regTRAP8_ADDRESS_HI 0xe84283 +#define regTRAP8_ADDRESS_HI_BASE_IDX 8 +#define regTRAP8_COMMAND 0xe84284 +#define regTRAP8_COMMAND_BASE_IDX 8 +#define regTRAP8_ADDRESS_LO_MASK 0xe84286 +#define regTRAP8_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP8_ADDRESS_HI_MASK 0xe84287 +#define regTRAP8_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP8_COMMAND_MASK 0xe84288 +#define regTRAP8_COMMAND_MASK_BASE_IDX 8 +#define regTRAP9_CONTROL0 0xe84290 +#define regTRAP9_CONTROL0_BASE_IDX 8 +#define regTRAP9_ADDRESS_LO 0xe84292 +#define regTRAP9_ADDRESS_LO_BASE_IDX 8 +#define regTRAP9_ADDRESS_HI 0xe84293 +#define regTRAP9_ADDRESS_HI_BASE_IDX 8 +#define regTRAP9_COMMAND 0xe84294 +#define regTRAP9_COMMAND_BASE_IDX 8 +#define regTRAP9_ADDRESS_LO_MASK 0xe84296 +#define regTRAP9_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP9_ADDRESS_HI_MASK 0xe84297 +#define regTRAP9_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP9_COMMAND_MASK 0xe84298 +#define regTRAP9_COMMAND_MASK_BASE_IDX 8 +#define regTRAP10_CONTROL0 0xe842a0 +#define regTRAP10_CONTROL0_BASE_IDX 8 +#define regTRAP10_ADDRESS_LO 0xe842a2 +#define regTRAP10_ADDRESS_LO_BASE_IDX 8 +#define regTRAP10_ADDRESS_HI 0xe842a3 +#define regTRAP10_ADDRESS_HI_BASE_IDX 8 +#define regTRAP10_COMMAND 0xe842a4 +#define regTRAP10_COMMAND_BASE_IDX 8 +#define regTRAP10_ADDRESS_LO_MASK 0xe842a6 +#define regTRAP10_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP10_ADDRESS_HI_MASK 0xe842a7 +#define regTRAP10_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP10_COMMAND_MASK 0xe842a8 +#define regTRAP10_COMMAND_MASK_BASE_IDX 8 +#define regTRAP11_CONTROL0 0xe842b0 +#define regTRAP11_CONTROL0_BASE_IDX 8 +#define regTRAP11_ADDRESS_LO 0xe842b2 +#define regTRAP11_ADDRESS_LO_BASE_IDX 8 +#define regTRAP11_ADDRESS_HI 0xe842b3 +#define regTRAP11_ADDRESS_HI_BASE_IDX 8 +#define regTRAP11_COMMAND 0xe842b4 +#define regTRAP11_COMMAND_BASE_IDX 8 +#define regTRAP11_ADDRESS_LO_MASK 0xe842b6 +#define regTRAP11_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP11_ADDRESS_HI_MASK 0xe842b7 +#define regTRAP11_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP11_COMMAND_MASK 0xe842b8 +#define regTRAP11_COMMAND_MASK_BASE_IDX 8 +#define regTRAP12_CONTROL0 0xe842c0 +#define regTRAP12_CONTROL0_BASE_IDX 8 +#define regTRAP12_ADDRESS_LO 0xe842c2 +#define regTRAP12_ADDRESS_LO_BASE_IDX 8 +#define regTRAP12_ADDRESS_HI 0xe842c3 +#define regTRAP12_ADDRESS_HI_BASE_IDX 8 +#define regTRAP12_COMMAND 0xe842c4 +#define regTRAP12_COMMAND_BASE_IDX 8 +#define regTRAP12_ADDRESS_LO_MASK 0xe842c6 +#define regTRAP12_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP12_ADDRESS_HI_MASK 0xe842c7 +#define regTRAP12_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP12_COMMAND_MASK 0xe842c8 +#define regTRAP12_COMMAND_MASK_BASE_IDX 8 +#define regTRAP13_CONTROL0 0xe842d0 +#define regTRAP13_CONTROL0_BASE_IDX 8 +#define regTRAP13_ADDRESS_LO 0xe842d2 +#define regTRAP13_ADDRESS_LO_BASE_IDX 8 +#define regTRAP13_ADDRESS_HI 0xe842d3 +#define regTRAP13_ADDRESS_HI_BASE_IDX 8 +#define regTRAP13_COMMAND 0xe842d4 +#define regTRAP13_COMMAND_BASE_IDX 8 +#define regTRAP13_ADDRESS_LO_MASK 0xe842d6 +#define regTRAP13_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP13_ADDRESS_HI_MASK 0xe842d7 +#define regTRAP13_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP13_COMMAND_MASK 0xe842d8 +#define regTRAP13_COMMAND_MASK_BASE_IDX 8 +#define regTRAP14_CONTROL0 0xe842e0 +#define regTRAP14_CONTROL0_BASE_IDX 8 +#define regTRAP14_ADDRESS_LO 0xe842e2 +#define regTRAP14_ADDRESS_LO_BASE_IDX 8 +#define regTRAP14_ADDRESS_HI 0xe842e3 +#define regTRAP14_ADDRESS_HI_BASE_IDX 8 +#define regTRAP14_COMMAND 0xe842e4 +#define regTRAP14_COMMAND_BASE_IDX 8 +#define regTRAP14_ADDRESS_LO_MASK 0xe842e6 +#define regTRAP14_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP14_ADDRESS_HI_MASK 0xe842e7 +#define regTRAP14_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP14_COMMAND_MASK 0xe842e8 +#define regTRAP14_COMMAND_MASK_BASE_IDX 8 +#define regTRAP15_CONTROL0 0xe842f0 +#define regTRAP15_CONTROL0_BASE_IDX 8 +#define regTRAP15_ADDRESS_LO 0xe842f2 +#define regTRAP15_ADDRESS_LO_BASE_IDX 8 +#define regTRAP15_ADDRESS_HI 0xe842f3 +#define regTRAP15_ADDRESS_HI_BASE_IDX 8 +#define regTRAP15_COMMAND 0xe842f4 +#define regTRAP15_COMMAND_BASE_IDX 8 +#define regTRAP15_ADDRESS_LO_MASK 0xe842f6 +#define regTRAP15_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP15_ADDRESS_HI_MASK 0xe842f7 +#define regTRAP15_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP15_COMMAND_MASK 0xe842f8 +#define regTRAP15_COMMAND_MASK_BASE_IDX 8 +#define regSB_COMMAND 0xe85000 +#define regSB_COMMAND_BASE_IDX 8 +#define regSB_SUB_BUS_NUMBER_LATENCY 0xe85001 +#define regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 +#define regSB_IO_BASE_LIMIT 0xe85002 +#define regSB_IO_BASE_LIMIT_BASE_IDX 8 +#define regSB_MEM_BASE_LIMIT 0xe85003 +#define regSB_MEM_BASE_LIMIT_BASE_IDX 8 +#define regSB_PREF_BASE_LIMIT 0xe85004 +#define regSB_PREF_BASE_LIMIT_BASE_IDX 8 +#define regSB_PREF_BASE_UPPER 0xe85005 +#define regSB_PREF_BASE_UPPER_BASE_IDX 8 +#define regSB_PREF_LIMIT_UPPER 0xe85006 +#define regSB_PREF_LIMIT_UPPER_BASE_IDX 8 +#define regSB_IO_BASE_LIMIT_HI 0xe85007 +#define regSB_IO_BASE_LIMIT_HI_BASE_IDX 8 +#define regSB_IRQ_BRIDGE_CNTL 0xe85008 +#define regSB_IRQ_BRIDGE_CNTL_BASE_IDX 8 +#define regSB_EXT_BRIDGE_CNTL 0xe85009 +#define regSB_EXT_BRIDGE_CNTL_BASE_IDX 8 +#define regSB_PMI_STATUS_CNTL 0xe8500a +#define regSB_PMI_STATUS_CNTL_BASE_IDX 8 +#define regSB_SLOT_CAP 0xe8500b +#define regSB_SLOT_CAP_BASE_IDX 8 +#define regSB_ROOT_CNTL 0xe8500c +#define regSB_ROOT_CNTL_BASE_IDX 8 +#define regSB_DEVICE_CNTL2 0xe8500d +#define regSB_DEVICE_CNTL2_BASE_IDX 8 +#define regMCA_SMN_INT_REQ_ADDR 0xe85020 +#define regMCA_SMN_INT_REQ_ADDR_BASE_IDX 8 +#define regMCA_SMN_INT_MCM_ADDR 0xe85021 +#define regMCA_SMN_INT_MCM_ADDR_BASE_IDX 8 +#define regMCA_SMN_INT_APERTUREID 0xe85022 +#define regMCA_SMN_INT_APERTUREID_BASE_IDX 8 +#define regMCA_SMN_INT_CONTROL 0xe85023 +#define regMCA_SMN_INT_CONTROL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_rascfg_ras_cfgdec +// base address: 0x13b20000 +#define regPARITY_CONTROL_0 0xe88000 +#define regPARITY_CONTROL_0_BASE_IDX 8 +#define regPARITY_CONTROL_1 0xe88001 +#define regPARITY_CONTROL_1_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_UNCORR_0 0xe88002 +#define regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_CORR_0 0xe88004 +#define regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_UCP_0 0xe88006 +#define regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX 8 +#define regRAS_GLOBAL_STATUS_LO 0xe88008 +#define regRAS_GLOBAL_STATUS_LO_BASE_IDX 8 +#define regRAS_GLOBAL_STATUS_HI 0xe88009 +#define regRAS_GLOBAL_STATUS_HI_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP0 0xe8800a +#define regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP1 0xe8800b +#define regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP2 0xe8800c +#define regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP3 0xe8800d +#define regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP4 0xe8800e +#define regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP5 0xe8800f +#define regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP6 0xe88010 +#define regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP7 0xe88011 +#define regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP10 0xe88014 +#define regPARITY_ERROR_STATUS_UNCORR_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP11 0xe88015 +#define regPARITY_ERROR_STATUS_UNCORR_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP12 0xe88016 +#define regPARITY_ERROR_STATUS_UNCORR_GRP12_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP13 0xe88017 +#define regPARITY_ERROR_STATUS_UNCORR_GRP13_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP14 0xe88018 +#define regPARITY_ERROR_STATUS_UNCORR_GRP14_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP15 0xe88019 +#define regPARITY_ERROR_STATUS_UNCORR_GRP15_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP16 0xe8801a +#define regPARITY_ERROR_STATUS_UNCORR_GRP16_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP0 0xe8801b +#define regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP1 0xe8801c +#define regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP2 0xe8801d +#define regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP3 0xe8801e +#define regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP4 0xe8801f +#define regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP5 0xe88020 +#define regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP6 0xe88021 +#define regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP7 0xe88022 +#define regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP10 0xe88025 +#define regPARITY_ERROR_STATUS_CORR_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP11 0xe88026 +#define regPARITY_ERROR_STATUS_CORR_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP12 0xe88027 +#define regPARITY_ERROR_STATUS_CORR_GRP12_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP13 0xe88028 +#define regPARITY_ERROR_STATUS_CORR_GRP13_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP14 0xe88029 +#define regPARITY_ERROR_STATUS_CORR_GRP14_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP15 0xe8802a +#define regPARITY_ERROR_STATUS_CORR_GRP15_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP16 0xe8802b +#define regPARITY_ERROR_STATUS_CORR_GRP16_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP17 0xe8802c +#define regPARITY_ERROR_STATUS_CORR_GRP17_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP0 0xe8802d +#define regPARITY_COUNTER_CORR_GRP0_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP1 0xe8802e +#define regPARITY_COUNTER_CORR_GRP1_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP2 0xe8802f +#define regPARITY_COUNTER_CORR_GRP2_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP3 0xe88030 +#define regPARITY_COUNTER_CORR_GRP3_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP4 0xe88031 +#define regPARITY_COUNTER_CORR_GRP4_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP5 0xe88032 +#define regPARITY_COUNTER_CORR_GRP5_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP6 0xe88033 +#define regPARITY_COUNTER_CORR_GRP6_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP7 0xe88034 +#define regPARITY_COUNTER_CORR_GRP7_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP10 0xe88037 +#define regPARITY_COUNTER_CORR_GRP10_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP11 0xe88038 +#define regPARITY_COUNTER_CORR_GRP11_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP12 0xe88039 +#define regPARITY_COUNTER_CORR_GRP12_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP13 0xe8803a +#define regPARITY_COUNTER_CORR_GRP13_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP14 0xe8803b +#define regPARITY_COUNTER_CORR_GRP14_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP15 0xe8803c +#define regPARITY_COUNTER_CORR_GRP15_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP16 0xe8803d +#define regPARITY_COUNTER_CORR_GRP16_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP17 0xe8803e +#define regPARITY_COUNTER_CORR_GRP17_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP0 0xe8803f +#define regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP1 0xe88040 +#define regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP2 0xe88041 +#define regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP3 0xe88042 +#define regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP4 0xe88043 +#define regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP5 0xe88044 +#define regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP6 0xe88045 +#define regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP7 0xe88046 +#define regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP10 0xe88049 +#define regPARITY_ERROR_STATUS_UCP_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP11 0xe8804a +#define regPARITY_ERROR_STATUS_UCP_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP12 0xe8804b +#define regPARITY_ERROR_STATUS_UCP_GRP12_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP0 0xe8804c +#define regPARITY_COUNTER_UCP_GRP0_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP1 0xe8804d +#define regPARITY_COUNTER_UCP_GRP1_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP2 0xe8804e +#define regPARITY_COUNTER_UCP_GRP2_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP3 0xe8804f +#define regPARITY_COUNTER_UCP_GRP3_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP4 0xe88050 +#define regPARITY_COUNTER_UCP_GRP4_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP5 0xe88051 +#define regPARITY_COUNTER_UCP_GRP5_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP6 0xe88052 +#define regPARITY_COUNTER_UCP_GRP6_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP7 0xe88053 +#define regPARITY_COUNTER_UCP_GRP7_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP10 0xe88056 +#define regPARITY_COUNTER_UCP_GRP10_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP11 0xe88057 +#define regPARITY_COUNTER_UCP_GRP11_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP12 0xe88058 +#define regPARITY_COUNTER_UCP_GRP12_BASE_IDX 8 +#define regMISC_SEVERITY_CONTROL 0xe88059 +#define regMISC_SEVERITY_CONTROL_BASE_IDX 8 +#define regMISC_RAS_CONTROL 0xe8805a +#define regMISC_RAS_CONTROL_BASE_IDX 8 +#define regRAS_SCRATCH_0 0xe8805b +#define regRAS_SCRATCH_0_BASE_IDX 8 +#define regRAS_SCRATCH_1 0xe8805c +#define regRAS_SCRATCH_1_BASE_IDX 8 +#define regErrEvent_ACTION_CONTROL 0xe8805d +#define regErrEvent_ACTION_CONTROL_BASE_IDX 8 +#define regParitySerr_ACTION_CONTROL 0xe8805e +#define regParitySerr_ACTION_CONTROL_BASE_IDX 8 +#define regParityFatal_ACTION_CONTROL 0xe8805f +#define regParityFatal_ACTION_CONTROL_BASE_IDX 8 +#define regParityNonFatal_ACTION_CONTROL 0xe88060 +#define regParityNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regParityCorr_ACTION_CONTROL 0xe88061 +#define regParityCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortASerr_ACTION_CONTROL 0xe88062 +#define regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntFatal_ACTION_CONTROL 0xe88063 +#define regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntNonFatal_ACTION_CONTROL 0xe88064 +#define regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntCorr_ACTION_CONTROL 0xe88065 +#define regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtFatal_ACTION_CONTROL 0xe88066 +#define regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtNonFatal_ACTION_CONTROL 0xe88067 +#define regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtCorr_ACTION_CONTROL 0xe88068 +#define regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAParityErr_ACTION_CONTROL 0xe88069 +#define regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBSerr_ACTION_CONTROL 0xe8806a +#define regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntFatal_ACTION_CONTROL 0xe8806b +#define regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntNonFatal_ACTION_CONTROL 0xe8806c +#define regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntCorr_ACTION_CONTROL 0xe8806d +#define regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtFatal_ACTION_CONTROL 0xe8806e +#define regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtNonFatal_ACTION_CONTROL 0xe8806f +#define regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtCorr_ACTION_CONTROL 0xe88070 +#define regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBParityErr_ACTION_CONTROL 0xe88071 +#define regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCSerr_ACTION_CONTROL 0xe88072 +#define regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntFatal_ACTION_CONTROL 0xe88073 +#define regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntNonFatal_ACTION_CONTROL 0xe88074 +#define regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntCorr_ACTION_CONTROL 0xe88075 +#define regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtFatal_ACTION_CONTROL 0xe88076 +#define regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtNonFatal_ACTION_CONTROL 0xe88077 +#define regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtCorr_ACTION_CONTROL 0xe88078 +#define regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCParityErr_ACTION_CONTROL 0xe88079 +#define regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDSerr_ACTION_CONTROL 0xe8807a +#define regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntFatal_ACTION_CONTROL 0xe8807b +#define regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntNonFatal_ACTION_CONTROL 0xe8807c +#define regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntCorr_ACTION_CONTROL 0xe8807d +#define regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtFatal_ACTION_CONTROL 0xe8807e +#define regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtNonFatal_ACTION_CONTROL 0xe8807f +#define regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtCorr_ACTION_CONTROL 0xe88080 +#define regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDParityErr_ACTION_CONTROL 0xe88081 +#define regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortESerr_ACTION_CONTROL 0xe88082 +#define regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntFatal_ACTION_CONTROL 0xe88083 +#define regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntNonFatal_ACTION_CONTROL 0xe88084 +#define regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntCorr_ACTION_CONTROL 0xe88085 +#define regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtFatal_ACTION_CONTROL 0xe88086 +#define regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtNonFatal_ACTION_CONTROL 0xe88087 +#define regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtCorr_ACTION_CONTROL 0xe88088 +#define regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEParityErr_ACTION_CONTROL 0xe88089 +#define regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFSerr_ACTION_CONTROL 0xe8808a +#define regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntFatal_ACTION_CONTROL 0xe8808b +#define regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntNonFatal_ACTION_CONTROL 0xe8808c +#define regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntCorr_ACTION_CONTROL 0xe8808d +#define regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtFatal_ACTION_CONTROL 0xe8808e +#define regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtNonFatal_ACTION_CONTROL 0xe8808f +#define regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtCorr_ACTION_CONTROL 0xe88090 +#define regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFParityErr_ACTION_CONTROL 0xe88091 +#define regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGSerr_ACTION_CONTROL 0xe88092 +#define regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntFatal_ACTION_CONTROL 0xe88093 +#define regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntNonFatal_ACTION_CONTROL 0xe88094 +#define regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntCorr_ACTION_CONTROL 0xe88095 +#define regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtFatal_ACTION_CONTROL 0xe88096 +#define regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtNonFatal_ACTION_CONTROL 0xe88097 +#define regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtCorr_ACTION_CONTROL 0xe88098 +#define regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGParityErr_ACTION_CONTROL 0xe88099 +#define regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortASerr_ACTION_CONTROL 0xe880ca +#define regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntFatal_ACTION_CONTROL 0xe880cb +#define regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntNonFatal_ACTION_CONTROL 0xe880cc +#define regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntCorr_ACTION_CONTROL 0xe880cd +#define regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtFatal_ACTION_CONTROL 0xe880ce +#define regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtNonFatal_ACTION_CONTROL 0xe880cf +#define regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtCorr_ACTION_CONTROL 0xe880d0 +#define regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAParityErr_ACTION_CONTROL 0xe880d1 +#define regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regSYNCFLOOD_STATUS 0xe88200 +#define regSYNCFLOOD_STATUS_BASE_IDX 8 +#define regNMI_STATUS 0xe88201 +#define regNMI_STATUS_BASE_IDX 8 +#define regPOISON_ACTION_CONTROL 0xe88205 +#define regPOISON_ACTION_CONTROL_BASE_IDX 8 +#define regINTERNAL_POISON_STATUS 0xe88206 +#define regINTERNAL_POISON_STATUS_BASE_IDX 8 +#define regINTERNAL_POISON_MASK 0xe88207 +#define regINTERNAL_POISON_MASK_BASE_IDX 8 +#define regEGRESS_POISON_STATUS_LO 0xe88208 +#define regEGRESS_POISON_STATUS_LO_BASE_IDX 8 +#define regEGRESS_POISON_STATUS_HI 0xe88209 +#define regEGRESS_POISON_STATUS_HI_BASE_IDX 8 +#define regEGRESS_POISON_MASK_LO 0xe8820a +#define regEGRESS_POISON_MASK_LO_BASE_IDX 8 +#define regEGRESS_POISON_MASK_HI 0xe8820b +#define regEGRESS_POISON_MASK_HI_BASE_IDX 8 +#define regEGRESS_POISON_SEVERITY_DOWN 0xe8820c +#define regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX 8 +#define regEGRESS_POISON_SEVERITY_UPPER 0xe8820d +#define regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX 8 +#define regAPML_STATUS 0xe88370 +#define regAPML_STATUS_BASE_IDX 8 +#define regAPML_CONTROL 0xe88371 +#define regAPML_CONTROL_BASE_IDX 8 +#define regAPML_TRIGGER 0xe88372 +#define regAPML_TRIGGER_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +// base address: 0x13b31000 +#define regNB_PCIE0DEVINDCFG0_STEERING_CNTL 0xe8c403 +#define regNB_PCIE0DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +// base address: 0x13b31400 +#define regNB_PCIE0DEVINDCFG1_STEERING_CNTL 0xe8c503 +#define regNB_PCIE0DEVINDCFG1_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +// base address: 0x13b31800 +#define regNB_PCIE0DEVINDCFG2_STEERING_CNTL 0xe8c603 +#define regNB_PCIE0DEVINDCFG2_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +// base address: 0x13b31c00 +#define regNB_PCIE0DEVINDCFG3_STEERING_CNTL 0xe8c703 +#define regNB_PCIE0DEVINDCFG3_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +// base address: 0x13b32000 +#define regNB_PCIE0DEVINDCFG4_STEERING_CNTL 0xe8c803 +#define regNB_PCIE0DEVINDCFG4_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +// base address: 0x13b32400 +#define regNB_PCIE0DEVINDCFG5_STEERING_CNTL 0xe8c903 +#define regNB_PCIE0DEVINDCFG5_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +// base address: 0x13b32800 +#define regNB_PCIE0DEVINDCFG6_STEERING_CNTL 0xe8ca03 +#define regNB_PCIE0DEVINDCFG6_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +// base address: 0x13b38000 +#define regNB_NBIF1DEVINDCFG0_STEERING_CNTL 0xe8e003 +#define regNB_NBIF1DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +// base address: 0x13b3c000 +#define regNB_INTSBDEVINDCFG0_STEERING_CNTL 0xe8f003 +#define regNB_INTSBDEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +// base address: 0x13b7d600 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9f5b7 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX 0xe9f5b8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA 0xe9f5b9 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +// base address: 0x13b7d700 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION 0xe9f5f7 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX 0xe9f5f8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA 0xe9f5f9 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +// base address: 0x13b7d800 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION 0xe9f637 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX 0xe9f638 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA 0xe9f639 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +// base address: 0x13b7d900 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION 0xe9f677 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX 0xe9f678 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA 0xe9f679 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +// base address: 0x13b7da00 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION 0xe9f6b7 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX 0xe9f6b8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA 0xe9f6b9 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +// base address: 0x13b7db00 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION 0xe9f6f7 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX 0xe9f6f8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA 0xe9f6f9 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +// base address: 0x13b7dc00 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION 0xe9f737 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX 0xe9f738 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA 0xe9f739 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +// base address: 0x13b7f200 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9fcb7 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX 0xe9fcb8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA 0xe9fcb9 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_iommu_l2a_l2acfg +// base address: 0x15700000 +#define regL2_PERF_CNTL_0 0x1580000 +#define regL2_PERF_CNTL_0_BASE_IDX 8 +#define regL2_PERF_COUNT_0 0x1580001 +#define regL2_PERF_COUNT_0_BASE_IDX 8 +#define regL2_PERF_COUNT_1 0x1580002 +#define regL2_PERF_COUNT_1_BASE_IDX 8 +#define regL2_PERF_CNTL_1 0x1580003 +#define regL2_PERF_CNTL_1_BASE_IDX 8 +#define regL2_PERF_COUNT_2 0x1580004 +#define regL2_PERF_COUNT_2_BASE_IDX 8 +#define regL2_PERF_COUNT_3 0x1580005 +#define regL2_PERF_COUNT_3_BASE_IDX 8 +#define regL2_STATUS_0 0x1580008 +#define regL2_STATUS_0_BASE_IDX 8 +#define regL2_CONTROL_0 0x158000c +#define regL2_CONTROL_0_BASE_IDX 8 +#define regL2_CONTROL_1 0x158000d +#define regL2_CONTROL_1_BASE_IDX 8 +#define regL2_DTC_CONTROL 0x1580010 +#define regL2_DTC_CONTROL_BASE_IDX 8 +#define regL2_DTC_HASH_CONTROL 0x1580011 +#define regL2_DTC_HASH_CONTROL_BASE_IDX 8 +#define regL2_DTC_WAY_CONTROL 0x1580012 +#define regL2_DTC_WAY_CONTROL_BASE_IDX 8 +#define regL2_ITC_CONTROL 0x1580014 +#define regL2_ITC_CONTROL_BASE_IDX 8 +#define regL2_ITC_HASH_CONTROL 0x1580015 +#define regL2_ITC_HASH_CONTROL_BASE_IDX 8 +#define regL2_ITC_WAY_CONTROL 0x1580016 +#define regL2_ITC_WAY_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_CONTROL 0x1580018 +#define regL2_PTC_A_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_HASH_CONTROL 0x1580019 +#define regL2_PTC_A_HASH_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_WAY_CONTROL 0x158001a +#define regL2_PTC_A_WAY_CONTROL_BASE_IDX 8 +#define regL2A_UPDATE_FILTER_CNTL 0x1580022 +#define regL2A_UPDATE_FILTER_CNTL_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_3 0x1580030 +#define regL2_ERR_RULE_CONTROL_3_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_4 0x1580031 +#define regL2_ERR_RULE_CONTROL_4_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_5 0x1580032 +#define regL2_ERR_RULE_CONTROL_5_BASE_IDX 8 +#define regL2_L2A_CK_GATE_CONTROL 0x1580033 +#define regL2_L2A_CK_GATE_CONTROL_BASE_IDX 8 +#define regL2_L2A_PGSIZE_CONTROL 0x1580034 +#define regL2_L2A_PGSIZE_CONTROL_BASE_IDX 8 +#define regL2_PWRGATE_CNTRL_REG_0 0x158003e +#define regL2_PWRGATE_CNTRL_REG_0_BASE_IDX 8 +#define regL2_PWRGATE_CNTRL_REG_3 0x1580041 +#define regL2_PWRGATE_CNTRL_REG_3_BASE_IDX 8 +#define regL2_ECO_CNTRL_0 0x1580042 +#define regL2_ECO_CNTRL_0_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_iommu_l2indx_l2indxcfg +// base address: 0x13f01000 +#define regL2_STATUS_1 0xf80448 +#define regL2_STATUS_1_BASE_IDX 8 +#define regL2_SB_LOCATION 0xf8044b +#define regL2_SB_LOCATION_BASE_IDX 8 +#define regL2_CONTROL_5 0xf8044c +#define regL2_CONTROL_5_BASE_IDX 8 +#define regL2_CONTROL_6 0xf8044f +#define regL2_CONTROL_6_BASE_IDX 8 +#define regL2_PDC_CONTROL 0xf80450 +#define regL2_PDC_CONTROL_BASE_IDX 8 +#define regL2_PDC_HASH_CONTROL 0xf80451 +#define regL2_PDC_HASH_CONTROL_BASE_IDX 8 +#define regL2_PDC_WAY_CONTROL 0xf80452 +#define regL2_PDC_WAY_CONTROL_BASE_IDX 8 +#define regL2B_UPDATE_FILTER_CNTL 0xf80453 +#define regL2B_UPDATE_FILTER_CNTL_BASE_IDX 8 +#define regL2_TW_CONTROL 0xf80454 +#define regL2_TW_CONTROL_BASE_IDX 8 +#define regL2_CP_CONTROL 0xf80456 +#define regL2_CP_CONTROL_BASE_IDX 8 +#define regL2_CP_CONTROL_1 0xf80457 +#define regL2_CP_CONTROL_1_BASE_IDX 8 +#define regL2_TW_CONTROL_1 0xf8045a +#define regL2_TW_CONTROL_1_BASE_IDX 8 +#define regL2_TW_CONTROL_2 0xf80461 +#define regL2_TW_CONTROL_2_BASE_IDX 8 +#define regL2_TW_CONTROL_3 0xf80462 +#define regL2_TW_CONTROL_3_BASE_IDX 8 +#define regL2_CREDIT_CONTROL_0 0xf80470 +#define regL2_CREDIT_CONTROL_0_BASE_IDX 8 +#define regL2_CREDIT_CONTROL_1 0xf80471 +#define regL2_CREDIT_CONTROL_1_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_0 0xf80480 +#define regL2_ERR_RULE_CONTROL_0_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_1 0xf80481 +#define regL2_ERR_RULE_CONTROL_1_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_2 0xf80482 +#define regL2_ERR_RULE_CONTROL_2_BASE_IDX 8 +#define regL2_L2B_CK_GATE_CONTROL 0xf80490 +#define regL2_L2B_CK_GATE_CONTROL_BASE_IDX 8 +#define regPPR_CONTROL 0xf80492 +#define regPPR_CONTROL_BASE_IDX 8 +#define regL2_L2B_PGSIZE_CONTROL 0xf80494 +#define regL2_L2B_PGSIZE_CONTROL_BASE_IDX 8 +#define regL2_PERF_CNTL_2 0xf80499 +#define regL2_PERF_CNTL_2_BASE_IDX 8 +#define regL2_PERF_COUNT_4 0xf8049a +#define regL2_PERF_COUNT_4_BASE_IDX 8 +#define regL2_PERF_COUNT_5 0xf8049b +#define regL2_PERF_COUNT_5_BASE_IDX 8 +#define regL2_PERF_CNTL_3 0xf8049c +#define regL2_PERF_CNTL_3_BASE_IDX 8 +#define regL2_PERF_COUNT_6 0xf8049d +#define regL2_PERF_COUNT_6_BASE_IDX 8 +#define regL2_PERF_COUNT_7 0xf8049e +#define regL2_PERF_COUNT_7_BASE_IDX 8 +#define regL2B_SDP_PARITY_ERROR_EN 0xf804a2 +#define regL2B_SDP_PARITY_ERROR_EN_BASE_IDX 8 +#define regL2_ECO_CNTRL_1 0xf804a3 +#define regL2_ECO_CNTRL_1_BASE_IDX 8 +#define regL2_CP_CONTROL_2 0xf804bf +#define regL2_CP_CONTROL_2_BASE_IDX 8 +#define regL2_CP_CONTROL_3 0xf804c0 +#define regL2_CP_CONTROL_3_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +// base address: 0x14300000 +#define regFEATURES_ENABLE 0x1080000 +#define regFEATURES_ENABLE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d +#define cfgIRQ_BRIDGE_CNTL 0x003e +#define cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV0_RC_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV0_RC_ROOT_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_RC_ROOT_CAP 0x0076 +#define cfgBIF_CFG_DEV0_RC_ROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV0_RC_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_RC_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x050c + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 4 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h new file mode 100644 index 000000000000..a22481e7bcdb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h @@ -0,0 +1,38900 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_7_9_0_SH_MASK_HEADER +#define _nbio_7_9_0_SH_MASK_HEADER + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +//BIF_BX0_PCIE_INDEX +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA +#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX2 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_DATA2 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX0_PCIE_INDEX_HI +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//BIF_BX0_PCIE_INDEX2_HI +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//BIF_BX0_SBIOS_SCRATCH_0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_1 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_2 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_3 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_1 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_2 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_3 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_4 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_5 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_6 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_7 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_8 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_9 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_10 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_11 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_12 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_13 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_14 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_BIOS_SCRATCH_15 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RLC_INTR_CNTL +//BIF_BX0_BIF_VCE_INTR_CNTL +//BIF_BX0_BIF_UVD_INTR_CNTL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_CNTL +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_1 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_2 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_3 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_4 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_5 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_6 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_7 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_8 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_9 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_10 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_11 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_12 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_13 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_14 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_DRIVER_SCRATCH_15 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_1 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_2 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_3 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_4 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_5 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_6 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_7 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_8 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_9 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_10 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_11 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_12 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_13 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_14 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_FW_SCRATCH_15 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_4 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_5 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_6 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_7 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_8 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_9 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_10 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_11 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_12 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_13 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_14 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX0_SBIOS_SCRATCH_15 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_0_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_0_DN_PCIE_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_0_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_0_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_0_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF0_MM_INDEX +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF0_MM_DATA +#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MM_INDEX_HI +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_DATA +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_RSMU_INDEX_HI +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT 0x0 +#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK 0x000000FFL + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +//BIF_BX0_CC_BIF_BX_STRAP0 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX0_CC_BIF_BX_PINSTRAP0 +//BIF_BX0_BIF_MM_INDACCESS_CNTL +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX0_BUS_CNTL +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX0_BIF_SCRATCH0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_SCRATCH1 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX0_BX_RESET_EN +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX0_MM_CFGREGS_CNTL +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX0_BX_RESET_CNTL +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX0_INTERRUPT_CNTL +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX0_INTERRUPT_CNTL2 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_CLKREQB_PAD_CNTL +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX0_BIF_FEATURES_CONTROL_MISC +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX0_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX0_BIF_DOORBELL_CNTL +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX0_BIF_DOORBELL_INT_CNTL +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX0_BIF_FB_EN +#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX0_BIF_INTR_CNTL +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX0_BIF_MST_TRANS_PENDING_VF +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX0_BACO_CNTL +#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX0_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIME0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER1 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX0_BIF_BACO_EXIT_TIMER2 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER3 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_BIF_BACO_EXIT_TIMER4 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX0_MEM_TYPE_CNTL +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX0_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX0_BIF_RB_CNTL +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX0_BIF_RB_BASE +#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX0_BIF_RB_RPTR +#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX0_BIF_RB_WPTR_ADDR_HI +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX0_BIF_RB_WPTR_ADDR_LO +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX0_MAILBOX_INDEX +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX0_BIF_MP1_INTR_CTRL +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX0_BIF_PERSTB_PAD_CNTL +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX0_BIF_PX_EN_PAD_CNTL +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX0_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX0_BIF_CLKREQB_PAD_CNTL +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX0_BIF_PWRBRK_PAD_CNTL +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_0_RCC_ERR_INT_CNTL +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_BACO_CNTL_MISC +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_0_RCC_RESET_EN +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_0_RCC_VDM_SUPPORT +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_0_RCC_GPUIOV_REGION +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_0_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_0_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_BUS_CNTL +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_0_RCC_CONFIG_CNTL +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_0_RCC_CONFIG_F0_BASE +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_0_RCC_XDMA_LO +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_XDMA_HI +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_0_RCC_BUSNUM_LIST0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_LIST1 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_0_RCC_HOST_BUSNUM +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_0_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_0_RCC_CMN_LINK_CNTL +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_0_RCC_MH_ARB_CNTL +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3 +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L +#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_STRAP0_RCC_BIF_STRAP0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP1 +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP2 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP0_RCC_BIF_STRAP3 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP4 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_BIF_STRAP5 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP0_RCC_BIF_STRAP6 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP0_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP25 +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF0_BIF_BME_STATUS +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF0_BIF_TRANS_PENDING +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF0_MAILBOX_CONTROL +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF0_MAILBOX_INT_CNTL +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF0_BIF_VMHV_MAILBOX +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF0_PARTITION_COMPUTE_CAP +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF0_PARTITION_MEM_CAP +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF0_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF0_PARTITION_MEM_STATUS +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT 0x0 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK 0x0000000FL +#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +//RCC_DEV0_EPF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +//GDC0_A2S_CNTL_CL0 +#define GDC0_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +#define GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC0_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +#define GDC0_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +#define GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC0_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +#define GDC0_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +#define GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC0_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L +#define GDC0_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC0_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC0_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC0_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L +#define GDC0_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L +#define GDC0_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC0_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC0_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L +#define GDC0_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L +#define GDC0_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC0_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC0_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC0_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK 0x70000000L +//GDC0_A2S_CNTL_CL1 +#define GDC0_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 +#define GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC0_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa +#define GDC0_A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc +#define GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC0_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 +#define GDC0_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 +#define GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC0_A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L +#define GDC0_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC0_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC0_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC0_A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000C00L +#define GDC0_A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L +#define GDC0_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC0_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC0_A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000C0000L +#define GDC0_A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L +#define GDC0_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC0_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC0_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC0_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK 0x70000000L +//GDC0_A2S_CNTL3_CL0 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT 0x0 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_PH_MASK 0x00000003L +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC0_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC0_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC0_A2S_CNTL3_CL1 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT 0x0 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_PH_MASK 0x00000003L +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC0_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC0_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC0_A2S_CNTL_SW0 +#define GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC0_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC0_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC0_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC0_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC0_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC0_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC0_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC0_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC0_A2S_CNTL_SW1 +#define GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC0_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC0_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC0_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC0_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC0_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC0_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC0_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC0_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC0_A2S_CNTL_SW2 +#define GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC0_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC0_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC0_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC0_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC0_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC0_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC0_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC0_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC0_A2S_TAG_ALLOC_0 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define GDC0_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//GDC0_A2S_TAG_ALLOC_1 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define GDC0_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//GDC0_A2S_MISC_CNTL +#define GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +#define GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3 +#define GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 +#define GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 +#define GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 +#define GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 +#define GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 +#define GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa +#define GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 +#define GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 +#define GDC0_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a +#define GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b +#define GDC0_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define GDC0_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L +#define GDC0_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L +#define GDC0_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L +#define GDC0_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L +#define GDC0_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +#define GDC0_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L +#define GDC0_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L +#define GDC0_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L +#define GDC0_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L +#define GDC0_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L +#define GDC0_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L +#define GDC0_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L +#define GDC0_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L +//GDC0_SHUB_REGS_IF_CTL +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC0_NGDC_MGCG_CTRL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xe +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00004000L +//GDC0_NGDC_RESERVED_0 +#define GDC0_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC0_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC0_NGDC_RESERVED_1 +#define GDC0_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC0_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC0_NBIF_GFX_DOORBELL_STATUS +#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//GDC0_ATDMA_MISC_CNTL +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC0_S2A_MISC_CNTL +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC0_NGDC_PG_MISC_CTRL +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10 +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define GDC0_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//GDC0_NGDC_PGMST_CTRL +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define GDC0_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//GDC0_NGDC_PGSLV_CTRL +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define GDC0_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_COMMAND +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_STATUS +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_LATENCY +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_HEADER +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BIST +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//PCIE_PAGE_REQ_ENH_CAP_LIST +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_PAGE_REQ_CNTL +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//PCIE_PAGE_REQ_STATUS +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//PCIE_SRIOV_ENH_CAP_LIST +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//PCIE_SRIOV_CAP +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//PCIE_SRIOV_CONTROL +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//PCIE_SRIOV_STATUS +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//PCIE_SRIOV_INITIAL_VFS +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_TOTAL_VFS +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//PCIE_SRIOV_NUM_VFS +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//PCIE_SRIOV_FUNC_DEP_LINK +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//PCIE_SRIOV_FIRST_VF_OFFSET +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//PCIE_SRIOV_VF_STRIDE +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//PCIE_SRIOV_VF_DEVICE_ID +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_1 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_2 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_3 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_4 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_BASE_ADDR_5 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK 0x000000FFL +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK 0x0000FF00L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK 0x00FF0000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK 0xFF000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_COMMAND +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_STATUS +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_REVISION_ID +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_LATENCY +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_HEADER +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BIST +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_CAP_PTR +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PMI_CAP +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_LINK_CAP +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC0_VENDOR_ID +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_DEVICE_ID +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_COMMAND +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC0_STATUS +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_REVISION_ID +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PROG_INTERFACE +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_SUB_CLASS +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_BASE_CLASS +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC0_CACHE_LINE +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_LATENCY +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC0_HEADER +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC0_BIST +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC0_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC0_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_CAP_PTR +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC0_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC0_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC0_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PMI_CAP +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC0_DEVICE_CAP +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC0_LINK_CAP +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC0_LINK_STATUS +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC0_SLOT_CNTL +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC0_SLOT_STATUS +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC0_ROOT_CNTL +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC0_ROOT_CAP +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC0_ROOT_STATUS +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC0_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_LINK_CAP2 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_LINK_CNTL2 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC0_LINK_STATUS2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC0_SLOT_CAP2 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC0_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC0_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_SSID_CAP +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC0_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_COMMAND +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_STATUS +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_LATENCY +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_HEADER +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BIST +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PMI_CAP +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN2SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN3SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN4SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN5SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN6SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__VCN7SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN8SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN9SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN10SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__VCN11SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX0SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX1SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX2SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__GFX3SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX4SCH_OFFSET_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX5SCH_OFFSET_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX6SCH_OFFSET_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__GFX7SCH_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0__DW0_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1__DW1_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2__DW2_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3__DW3_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4__DW4_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5__DW5_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6__DW6_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7__DW7_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8__DW8_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE__ENGA_A7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B0_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B2_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B3_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_CMD_COMPLETE_INTR_EN_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B4_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_CMD_COMPLETE_INTR_EN_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_HANG_NEED_FLR_INTR_EN_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B5_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_CMD_COMPLETE_INTR_EN_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_SELF_RECOVERED_INTR_EN_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_HANG_NEED_FLR_INTR_EN_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B6_VM_BUSY_TRANSITION_INTR_EN_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_CMD_COMPLETE_INTR_EN_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_SELF_RECOVERED_INTR_EN_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_HANG_NEED_FLR_INTR_EN_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE__ENGB_B7_VM_BUSY_TRANSITION_INTR_EN_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_CMD_COMPLETE_INTR_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B8_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_CMD_COMPLETE_INTR_EN_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_HANG_NEED_FLR_INTR_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B9_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_CMD_COMPLETE_INTR_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B10_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_CMD_COMPLETE_INTR_EN_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE__ENGB_B11_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS__ENGA_A7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1b +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1d +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x1e +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B0_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B2_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B3_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B4_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_CMD_COMPLETE_INTR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_HANG_NEED_FLR_INTR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B5_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_CMD_COMPLETE_INTR_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_HANG_NEED_FLR_INTR_STATUS_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B6_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x08000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_CMD_COMPLETE_INTR_STATUS_MASK 0x10000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x20000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_HANG_NEED_FLR_INTR_STATUS_MASK 0x40000000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS__ENGB_B7_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B8_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_CMD_COMPLETE_INTR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B9_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B10_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS__ENGB_B11_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +//BIF_CFG_DEV0_EPF1_0_VENDOR_ID +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_DEVICE_ID +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_COMMAND +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_STATUS +#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_REVISION_ID +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_SUB_CLASS +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_BASE_CLASS +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_CACHE_LINE +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_LATENCY +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_HEADER +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BIST +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF1_0_CAP_PTR +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MIN_GRANT +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L +#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L +//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PMI_CAP +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF1_0_LINK_CAP +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_MSIX_PBA +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L +//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L +//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_RCCPORTDEC +//RCC_DEV0_1_RCC_VDM_SUPPORT +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_1_RCC_BUS_CNTL +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_1_RCC_CMN_LINK_CNTL +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_1_RCC_MH_ARB_CNTL +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +//RCC_EP_DEV0_1_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_1_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +//RCC_DWN_DEV0_1_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_1_DN_PCIE_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_1_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK 0x000003FFL +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK 0x00001C00L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK 0x00008000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK 0x03FF0000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK 0x1C000000L +#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK 0x80000000L +//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK 0x00000100L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK 0x00000001L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK 0x00000002L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK 0x00000004L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK 0x00000008L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK 0x00000010L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK 0x00000020L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK 0x00000040L +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00000080L +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK 0xFFFFFFFFL +//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK 0x00000007L +#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXTDEC +//PCIEMSIX_VECT0_ADDR_LO +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT0_ADDR_HI +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT0_MSG_DATA +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT0_CONTROL +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT1_ADDR_LO +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT1_ADDR_HI +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT1_MSG_DATA +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT1_CONTROL +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT2_ADDR_LO +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT2_ADDR_HI +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT2_MSG_DATA +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT2_CONTROL +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT3_ADDR_LO +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT3_ADDR_HI +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT3_MSG_DATA +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT3_CONTROL +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT4_ADDR_LO +#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT4_ADDR_HI +#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT4_MSG_DATA +#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT4_CONTROL +#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT5_ADDR_LO +#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT5_ADDR_HI +#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT5_MSG_DATA +#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT5_CONTROL +#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT6_ADDR_LO +#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT6_ADDR_HI +#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT6_MSG_DATA +#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT6_CONTROL +#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT7_ADDR_LO +#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT7_ADDR_HI +#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT7_MSG_DATA +#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT7_CONTROL +#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT8_ADDR_LO +#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT8_ADDR_HI +#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT8_MSG_DATA +#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT8_CONTROL +#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT9_ADDR_LO +#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT9_ADDR_HI +#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT9_MSG_DATA +#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT9_CONTROL +#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT10_ADDR_LO +#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT10_ADDR_HI +#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT10_MSG_DATA +#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT10_CONTROL +#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT11_ADDR_LO +#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT11_ADDR_HI +#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT11_MSG_DATA +#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT11_CONTROL +#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT12_ADDR_LO +#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT12_ADDR_HI +#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT12_MSG_DATA +#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT12_CONTROL +#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT13_ADDR_LO +#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT13_ADDR_HI +#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT13_MSG_DATA +#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT13_CONTROL +#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT14_ADDR_LO +#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT14_ADDR_HI +#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT14_MSG_DATA +#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT14_CONTROL +#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT15_ADDR_LO +#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT15_ADDR_HI +#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT15_MSG_DATA +#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT15_CONTROL +#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT16_ADDR_LO +#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT16_ADDR_HI +#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT16_MSG_DATA +#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT16_CONTROL +#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT17_ADDR_LO +#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT17_ADDR_HI +#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT17_MSG_DATA +#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT17_CONTROL +#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT18_ADDR_LO +#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT18_ADDR_HI +#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT18_MSG_DATA +#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT18_CONTROL +#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT19_ADDR_LO +#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT19_ADDR_HI +#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT19_MSG_DATA +#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT19_CONTROL +#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT20_ADDR_LO +#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT20_ADDR_HI +#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT20_MSG_DATA +#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT20_CONTROL +#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT21_ADDR_LO +#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT21_ADDR_HI +#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT21_MSG_DATA +#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT21_CONTROL +#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT22_ADDR_LO +#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT22_ADDR_HI +#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT22_MSG_DATA +#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT22_CONTROL +#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT23_ADDR_LO +#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT23_ADDR_HI +#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT23_MSG_DATA +#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT23_CONTROL +#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT24_ADDR_LO +#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT24_ADDR_HI +#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT24_MSG_DATA +#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT24_CONTROL +#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT25_ADDR_LO +#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT25_ADDR_HI +#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT25_MSG_DATA +#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT25_CONTROL +#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT26_ADDR_LO +#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT26_ADDR_HI +#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT26_MSG_DATA +#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT26_CONTROL +#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT27_ADDR_LO +#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT27_ADDR_HI +#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT27_MSG_DATA +#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT27_CONTROL +#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT28_ADDR_LO +#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT28_ADDR_HI +#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT28_MSG_DATA +#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT28_CONTROL +#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT29_ADDR_LO +#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT29_ADDR_HI +#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT29_MSG_DATA +#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT29_CONTROL +#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT30_ADDR_LO +#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT30_ADDR_HI +#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT30_MSG_DATA +#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT30_CONTROL +#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT31_ADDR_LO +#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT31_ADDR_HI +#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT31_MSG_DATA +#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT31_CONTROL +#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT32_ADDR_LO +#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT32_ADDR_HI +#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT32_MSG_DATA +#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT32_CONTROL +#define PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT33_ADDR_LO +#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT33_ADDR_HI +#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT33_MSG_DATA +#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT33_CONTROL +#define PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT34_ADDR_LO +#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT34_ADDR_HI +#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT34_MSG_DATA +#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT34_CONTROL +#define PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT35_ADDR_LO +#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT35_ADDR_HI +#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT35_MSG_DATA +#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT35_CONTROL +#define PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT36_ADDR_LO +#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT36_ADDR_HI +#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT36_MSG_DATA +#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT36_CONTROL +#define PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT37_ADDR_LO +#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT37_ADDR_HI +#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT37_MSG_DATA +#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT37_CONTROL +#define PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT38_ADDR_LO +#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT38_ADDR_HI +#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT38_MSG_DATA +#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT38_CONTROL +#define PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT39_ADDR_LO +#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT39_ADDR_HI +#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT39_MSG_DATA +#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT39_CONTROL +#define PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT40_ADDR_LO +#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT40_ADDR_HI +#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT40_MSG_DATA +#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT40_CONTROL +#define PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT41_ADDR_LO +#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT41_ADDR_HI +#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT41_MSG_DATA +#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT41_CONTROL +#define PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT42_ADDR_LO +#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT42_ADDR_HI +#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT42_MSG_DATA +#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT42_CONTROL +#define PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT43_ADDR_LO +#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT43_ADDR_HI +#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT43_MSG_DATA +#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT43_CONTROL +#define PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT44_ADDR_LO +#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT44_ADDR_HI +#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT44_MSG_DATA +#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT44_CONTROL +#define PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT45_ADDR_LO +#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT45_ADDR_HI +#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT45_MSG_DATA +#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT45_CONTROL +#define PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT46_ADDR_LO +#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT46_ADDR_HI +#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT46_MSG_DATA +#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT46_CONTROL +#define PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT47_ADDR_LO +#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT47_ADDR_HI +#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT47_MSG_DATA +#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT47_CONTROL +#define PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT48_ADDR_LO +#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT48_ADDR_HI +#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT48_MSG_DATA +#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT48_CONTROL +#define PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT49_ADDR_LO +#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT49_ADDR_HI +#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT49_MSG_DATA +#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT49_CONTROL +#define PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT50_ADDR_LO +#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT50_ADDR_HI +#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT50_MSG_DATA +#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT50_CONTROL +#define PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT51_ADDR_LO +#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT51_ADDR_HI +#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT51_MSG_DATA +#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT51_CONTROL +#define PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT52_ADDR_LO +#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT52_ADDR_HI +#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT52_MSG_DATA +#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT52_CONTROL +#define PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT53_ADDR_LO +#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT53_ADDR_HI +#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT53_MSG_DATA +#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT53_CONTROL +#define PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT54_ADDR_LO +#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT54_ADDR_HI +#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT54_MSG_DATA +#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT54_CONTROL +#define PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT55_ADDR_LO +#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT55_ADDR_HI +#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT55_MSG_DATA +#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT55_CONTROL +#define PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT56_ADDR_LO +#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT56_ADDR_HI +#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT56_MSG_DATA +#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT56_CONTROL +#define PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT57_ADDR_LO +#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT57_ADDR_HI +#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT57_MSG_DATA +#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT57_CONTROL +#define PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT58_ADDR_LO +#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT58_ADDR_HI +#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT58_MSG_DATA +#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT58_CONTROL +#define PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT59_ADDR_LO +#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT59_ADDR_HI +#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT59_MSG_DATA +#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT59_CONTROL +#define PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT60_ADDR_LO +#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT60_ADDR_HI +#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT60_MSG_DATA +#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT60_CONTROL +#define PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT61_ADDR_LO +#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT61_ADDR_HI +#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT61_MSG_DATA +#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT61_CONTROL +#define PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT62_ADDR_LO +#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT62_ADDR_HI +#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT62_MSG_DATA +#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT62_CONTROL +#define PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT63_ADDR_LO +#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT63_ADDR_HI +#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT63_MSG_DATA +#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT63_CONTROL +#define PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT64_ADDR_LO +#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT64_ADDR_HI +#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT64_MSG_DATA +#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT64_CONTROL +#define PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT65_ADDR_LO +#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT65_ADDR_HI +#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT65_MSG_DATA +#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT65_CONTROL +#define PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT66_ADDR_LO +#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT66_ADDR_HI +#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT66_MSG_DATA +#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT66_CONTROL +#define PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT67_ADDR_LO +#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT67_ADDR_HI +#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT67_MSG_DATA +#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT67_CONTROL +#define PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT68_ADDR_LO +#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT68_ADDR_HI +#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT68_MSG_DATA +#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT68_CONTROL +#define PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT69_ADDR_LO +#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT69_ADDR_HI +#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT69_MSG_DATA +#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT69_CONTROL +#define PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT70_ADDR_LO +#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT70_ADDR_HI +#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT70_MSG_DATA +#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT70_CONTROL +#define PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT71_ADDR_LO +#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT71_ADDR_HI +#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT71_MSG_DATA +#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT71_CONTROL +#define PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT72_ADDR_LO +#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT72_ADDR_HI +#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT72_MSG_DATA +#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT72_CONTROL +#define PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT73_ADDR_LO +#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT73_ADDR_HI +#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT73_MSG_DATA +#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT73_CONTROL +#define PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT74_ADDR_LO +#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT74_ADDR_HI +#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT74_MSG_DATA +#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT74_CONTROL +#define PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT75_ADDR_LO +#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT75_ADDR_HI +#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT75_MSG_DATA +#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT75_CONTROL +#define PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT76_ADDR_LO +#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT76_ADDR_HI +#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT76_MSG_DATA +#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT76_CONTROL +#define PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT77_ADDR_LO +#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT77_ADDR_HI +#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT77_MSG_DATA +#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT77_CONTROL +#define PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT78_ADDR_LO +#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT78_ADDR_HI +#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT78_MSG_DATA +#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT78_CONTROL +#define PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT79_ADDR_LO +#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT79_ADDR_HI +#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT79_MSG_DATA +#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT79_CONTROL +#define PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT80_ADDR_LO +#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT80_ADDR_HI +#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT80_MSG_DATA +#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT80_CONTROL +#define PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT81_ADDR_LO +#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT81_ADDR_HI +#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT81_MSG_DATA +#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT81_CONTROL +#define PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT82_ADDR_LO +#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT82_ADDR_HI +#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT82_MSG_DATA +#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT82_CONTROL +#define PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT83_ADDR_LO +#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT83_ADDR_HI +#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT83_MSG_DATA +#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT83_CONTROL +#define PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT84_ADDR_LO +#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT84_ADDR_HI +#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT84_MSG_DATA +#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT84_CONTROL +#define PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT85_ADDR_LO +#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT85_ADDR_HI +#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT85_MSG_DATA +#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT85_CONTROL +#define PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT86_ADDR_LO +#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT86_ADDR_HI +#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT86_MSG_DATA +#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT86_CONTROL +#define PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT87_ADDR_LO +#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT87_ADDR_HI +#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT87_MSG_DATA +#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT87_CONTROL +#define PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT88_ADDR_LO +#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT88_ADDR_HI +#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT88_MSG_DATA +#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT88_CONTROL +#define PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT89_ADDR_LO +#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT89_ADDR_HI +#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT89_MSG_DATA +#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT89_CONTROL +#define PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT90_ADDR_LO +#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT90_ADDR_HI +#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT90_MSG_DATA +#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT90_CONTROL +#define PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT91_ADDR_LO +#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT91_ADDR_HI +#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT91_MSG_DATA +#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT91_CONTROL +#define PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT92_ADDR_LO +#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT92_ADDR_HI +#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT92_MSG_DATA +#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT92_CONTROL +#define PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT93_ADDR_LO +#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT93_ADDR_HI +#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT93_MSG_DATA +#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT93_CONTROL +#define PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT94_ADDR_LO +#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT94_ADDR_HI +#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT94_MSG_DATA +#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT94_CONTROL +#define PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT95_ADDR_LO +#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT95_ADDR_HI +#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT95_MSG_DATA +#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT95_CONTROL +#define PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT96_ADDR_LO +#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT96_ADDR_HI +#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT96_MSG_DATA +#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT96_CONTROL +#define PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT97_ADDR_LO +#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT97_ADDR_HI +#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT97_MSG_DATA +#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT97_CONTROL +#define PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT98_ADDR_LO +#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT98_ADDR_HI +#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT98_MSG_DATA +#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT98_CONTROL +#define PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT99_ADDR_LO +#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT99_ADDR_HI +#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT99_MSG_DATA +#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT99_CONTROL +#define PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT100_ADDR_LO +#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT100_ADDR_HI +#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT100_MSG_DATA +#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT100_CONTROL +#define PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT101_ADDR_LO +#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT101_ADDR_HI +#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT101_MSG_DATA +#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT101_CONTROL +#define PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT102_ADDR_LO +#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT102_ADDR_HI +#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT102_MSG_DATA +#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT102_CONTROL +#define PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT103_ADDR_LO +#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT103_ADDR_HI +#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT103_MSG_DATA +#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT103_CONTROL +#define PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT104_ADDR_LO +#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT104_ADDR_HI +#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT104_MSG_DATA +#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT104_CONTROL +#define PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT105_ADDR_LO +#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT105_ADDR_HI +#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT105_MSG_DATA +#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT105_CONTROL +#define PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT106_ADDR_LO +#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT106_ADDR_HI +#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT106_MSG_DATA +#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT106_CONTROL +#define PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT107_ADDR_LO +#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT107_ADDR_HI +#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT107_MSG_DATA +#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT107_CONTROL +#define PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT108_ADDR_LO +#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT108_ADDR_HI +#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT108_MSG_DATA +#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT108_CONTROL +#define PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT109_ADDR_LO +#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT109_ADDR_HI +#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT109_MSG_DATA +#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT109_CONTROL +#define PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT110_ADDR_LO +#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT110_ADDR_HI +#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT110_MSG_DATA +#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT110_CONTROL +#define PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT111_ADDR_LO +#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT111_ADDR_HI +#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT111_MSG_DATA +#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT111_CONTROL +#define PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT112_ADDR_LO +#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT112_ADDR_HI +#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT112_MSG_DATA +#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT112_CONTROL +#define PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT113_ADDR_LO +#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT113_ADDR_HI +#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT113_MSG_DATA +#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT113_CONTROL +#define PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT114_ADDR_LO +#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT114_ADDR_HI +#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT114_MSG_DATA +#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT114_CONTROL +#define PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT115_ADDR_LO +#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT115_ADDR_HI +#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT115_MSG_DATA +#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT115_CONTROL +#define PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT116_ADDR_LO +#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT116_ADDR_HI +#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT116_MSG_DATA +#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT116_CONTROL +#define PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT117_ADDR_LO +#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT117_ADDR_HI +#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT117_MSG_DATA +#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT117_CONTROL +#define PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT118_ADDR_LO +#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT118_ADDR_HI +#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT118_MSG_DATA +#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT118_CONTROL +#define PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT119_ADDR_LO +#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT119_ADDR_HI +#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT119_MSG_DATA +#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT119_CONTROL +#define PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT120_ADDR_LO +#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT120_ADDR_HI +#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT120_MSG_DATA +#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT120_CONTROL +#define PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT121_ADDR_LO +#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT121_ADDR_HI +#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT121_MSG_DATA +#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT121_CONTROL +#define PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT122_ADDR_LO +#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT122_ADDR_HI +#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT122_MSG_DATA +#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT122_CONTROL +#define PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT123_ADDR_LO +#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT123_ADDR_HI +#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT123_MSG_DATA +#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT123_CONTROL +#define PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT124_ADDR_LO +#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT124_ADDR_HI +#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT124_MSG_DATA +#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT124_CONTROL +#define PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT125_ADDR_LO +#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT125_ADDR_HI +#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT125_MSG_DATA +#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT125_CONTROL +#define PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT126_ADDR_LO +#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT126_ADDR_HI +#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT126_MSG_DATA +#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT126_CONTROL +#define PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT127_ADDR_LO +#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT127_ADDR_HI +#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT127_MSG_DATA +#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT127_CONTROL +#define PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT128_ADDR_LO +#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT128_ADDR_HI +#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT128_MSG_DATA +#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT128_CONTROL +#define PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT129_ADDR_LO +#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT129_ADDR_HI +#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT129_MSG_DATA +#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT129_CONTROL +#define PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT130_ADDR_LO +#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT130_ADDR_HI +#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT130_MSG_DATA +#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT130_CONTROL +#define PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT131_ADDR_LO +#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT131_ADDR_HI +#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT131_MSG_DATA +#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT131_CONTROL +#define PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT132_ADDR_LO +#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT132_ADDR_HI +#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT132_MSG_DATA +#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT132_CONTROL +#define PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT133_ADDR_LO +#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT133_ADDR_HI +#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT133_MSG_DATA +#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT133_CONTROL +#define PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT134_ADDR_LO +#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT134_ADDR_HI +#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT134_MSG_DATA +#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT134_CONTROL +#define PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT135_ADDR_LO +#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT135_ADDR_HI +#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT135_MSG_DATA +#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT135_CONTROL +#define PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT136_ADDR_LO +#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT136_ADDR_HI +#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT136_MSG_DATA +#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT136_CONTROL +#define PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT137_ADDR_LO +#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT137_ADDR_HI +#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT137_MSG_DATA +#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT137_CONTROL +#define PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT138_ADDR_LO +#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT138_ADDR_HI +#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT138_MSG_DATA +#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT138_CONTROL +#define PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT139_ADDR_LO +#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT139_ADDR_HI +#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT139_MSG_DATA +#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT139_CONTROL +#define PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT140_ADDR_LO +#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT140_ADDR_HI +#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT140_MSG_DATA +#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT140_CONTROL +#define PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT141_ADDR_LO +#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT141_ADDR_HI +#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT141_MSG_DATA +#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT141_CONTROL +#define PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT142_ADDR_LO +#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT142_ADDR_HI +#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT142_MSG_DATA +#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT142_CONTROL +#define PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT143_ADDR_LO +#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT143_ADDR_HI +#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT143_MSG_DATA +#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT143_CONTROL +#define PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT144_ADDR_LO +#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT144_ADDR_HI +#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT144_MSG_DATA +#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT144_CONTROL +#define PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT145_ADDR_LO +#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT145_ADDR_HI +#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT145_MSG_DATA +#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT145_CONTROL +#define PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT146_ADDR_LO +#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT146_ADDR_HI +#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT146_MSG_DATA +#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT146_CONTROL +#define PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT147_ADDR_LO +#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT147_ADDR_HI +#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT147_MSG_DATA +#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT147_CONTROL +#define PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT148_ADDR_LO +#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT148_ADDR_HI +#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT148_MSG_DATA +#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT148_CONTROL +#define PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT149_ADDR_LO +#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT149_ADDR_HI +#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT149_MSG_DATA +#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT149_CONTROL +#define PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT150_ADDR_LO +#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT150_ADDR_HI +#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT150_MSG_DATA +#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT150_CONTROL +#define PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT151_ADDR_LO +#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT151_ADDR_HI +#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT151_MSG_DATA +#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT151_CONTROL +#define PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT152_ADDR_LO +#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT152_ADDR_HI +#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT152_MSG_DATA +#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT152_CONTROL +#define PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT153_ADDR_LO +#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT153_ADDR_HI +#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT153_MSG_DATA +#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT153_CONTROL +#define PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT154_ADDR_LO +#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT154_ADDR_HI +#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT154_MSG_DATA +#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT154_CONTROL +#define PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT155_ADDR_LO +#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT155_ADDR_HI +#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT155_MSG_DATA +#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT155_CONTROL +#define PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT156_ADDR_LO +#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT156_ADDR_HI +#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT156_MSG_DATA +#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT156_CONTROL +#define PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT157_ADDR_LO +#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT157_ADDR_HI +#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT157_MSG_DATA +#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT157_CONTROL +#define PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT158_ADDR_LO +#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT158_ADDR_HI +#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT158_MSG_DATA +#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT158_CONTROL +#define PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT159_ADDR_LO +#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT159_ADDR_HI +#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT159_MSG_DATA +#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT159_CONTROL +#define PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT160_ADDR_LO +#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT160_ADDR_HI +#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT160_MSG_DATA +#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT160_CONTROL +#define PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT161_ADDR_LO +#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT161_ADDR_HI +#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT161_MSG_DATA +#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT161_CONTROL +#define PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT162_ADDR_LO +#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT162_ADDR_HI +#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT162_MSG_DATA +#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT162_CONTROL +#define PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT163_ADDR_LO +#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT163_ADDR_HI +#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT163_MSG_DATA +#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT163_CONTROL +#define PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT164_ADDR_LO +#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT164_ADDR_HI +#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT164_MSG_DATA +#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT164_CONTROL +#define PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT165_ADDR_LO +#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT165_ADDR_HI +#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT165_MSG_DATA +#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT165_CONTROL +#define PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT166_ADDR_LO +#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT166_ADDR_HI +#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT166_MSG_DATA +#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT166_CONTROL +#define PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT167_ADDR_LO +#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT167_ADDR_HI +#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT167_MSG_DATA +#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT167_CONTROL +#define PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT168_ADDR_LO +#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT168_ADDR_HI +#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT168_MSG_DATA +#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT168_CONTROL +#define PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT169_ADDR_LO +#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT169_ADDR_HI +#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT169_MSG_DATA +#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT169_CONTROL +#define PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT170_ADDR_LO +#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT170_ADDR_HI +#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT170_MSG_DATA +#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT170_CONTROL +#define PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT171_ADDR_LO +#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT171_ADDR_HI +#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT171_MSG_DATA +#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT171_CONTROL +#define PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT172_ADDR_LO +#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT172_ADDR_HI +#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT172_MSG_DATA +#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT172_CONTROL +#define PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT173_ADDR_LO +#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT173_ADDR_HI +#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT173_MSG_DATA +#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT173_CONTROL +#define PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT174_ADDR_LO +#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT174_ADDR_HI +#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT174_MSG_DATA +#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT174_CONTROL +#define PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT175_ADDR_LO +#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT175_ADDR_HI +#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT175_MSG_DATA +#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT175_CONTROL +#define PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT176_ADDR_LO +#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT176_ADDR_HI +#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT176_MSG_DATA +#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT176_CONTROL +#define PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT177_ADDR_LO +#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT177_ADDR_HI +#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT177_MSG_DATA +#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT177_CONTROL +#define PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT178_ADDR_LO +#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT178_ADDR_HI +#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT178_MSG_DATA +#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT178_CONTROL +#define PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT179_ADDR_LO +#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT179_ADDR_HI +#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT179_MSG_DATA +#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT179_CONTROL +#define PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT180_ADDR_LO +#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT180_ADDR_HI +#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT180_MSG_DATA +#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT180_CONTROL +#define PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT181_ADDR_LO +#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT181_ADDR_HI +#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT181_MSG_DATA +#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT181_CONTROL +#define PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT182_ADDR_LO +#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT182_ADDR_HI +#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT182_MSG_DATA +#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT182_CONTROL +#define PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT183_ADDR_LO +#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT183_ADDR_HI +#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT183_MSG_DATA +#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT183_CONTROL +#define PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT184_ADDR_LO +#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT184_ADDR_HI +#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT184_MSG_DATA +#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT184_CONTROL +#define PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT185_ADDR_LO +#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT185_ADDR_HI +#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT185_MSG_DATA +#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT185_CONTROL +#define PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT186_ADDR_LO +#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT186_ADDR_HI +#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT186_MSG_DATA +#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT186_CONTROL +#define PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT187_ADDR_LO +#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT187_ADDR_HI +#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT187_MSG_DATA +#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT187_CONTROL +#define PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT188_ADDR_LO +#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT188_ADDR_HI +#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT188_MSG_DATA +#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT188_CONTROL +#define PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT189_ADDR_LO +#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT189_ADDR_HI +#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT189_MSG_DATA +#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT189_CONTROL +#define PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT190_ADDR_LO +#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT190_ADDR_HI +#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT190_MSG_DATA +#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT190_CONTROL +#define PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT191_ADDR_LO +#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT191_ADDR_HI +#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT191_MSG_DATA +#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT191_CONTROL +#define PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT192_ADDR_LO +#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT192_ADDR_HI +#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT192_MSG_DATA +#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT192_CONTROL +#define PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT193_ADDR_LO +#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT193_ADDR_HI +#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT193_MSG_DATA +#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT193_CONTROL +#define PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT194_ADDR_LO +#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT194_ADDR_HI +#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT194_MSG_DATA +#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT194_CONTROL +#define PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT195_ADDR_LO +#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT195_ADDR_HI +#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT195_MSG_DATA +#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT195_CONTROL +#define PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT196_ADDR_LO +#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT196_ADDR_HI +#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT196_MSG_DATA +#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT196_CONTROL +#define PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT197_ADDR_LO +#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT197_ADDR_HI +#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT197_MSG_DATA +#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT197_CONTROL +#define PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT198_ADDR_LO +#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT198_ADDR_HI +#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT198_MSG_DATA +#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT198_CONTROL +#define PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT199_ADDR_LO +#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT199_ADDR_HI +#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT199_MSG_DATA +#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT199_CONTROL +#define PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT200_ADDR_LO +#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT200_ADDR_HI +#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT200_MSG_DATA +#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT200_CONTROL +#define PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT201_ADDR_LO +#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT201_ADDR_HI +#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT201_MSG_DATA +#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT201_CONTROL +#define PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT202_ADDR_LO +#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT202_ADDR_HI +#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT202_MSG_DATA +#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT202_CONTROL +#define PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT203_ADDR_LO +#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT203_ADDR_HI +#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT203_MSG_DATA +#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT203_CONTROL +#define PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT204_ADDR_LO +#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT204_ADDR_HI +#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT204_MSG_DATA +#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT204_CONTROL +#define PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT205_ADDR_LO +#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT205_ADDR_HI +#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT205_MSG_DATA +#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT205_CONTROL +#define PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT206_ADDR_LO +#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT206_ADDR_HI +#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT206_MSG_DATA +#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT206_CONTROL +#define PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT207_ADDR_LO +#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT207_ADDR_HI +#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT207_MSG_DATA +#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT207_CONTROL +#define PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT208_ADDR_LO +#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT208_ADDR_HI +#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT208_MSG_DATA +#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT208_CONTROL +#define PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT209_ADDR_LO +#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT209_ADDR_HI +#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT209_MSG_DATA +#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT209_CONTROL +#define PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT210_ADDR_LO +#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT210_ADDR_HI +#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT210_MSG_DATA +#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT210_CONTROL +#define PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT211_ADDR_LO +#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT211_ADDR_HI +#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT211_MSG_DATA +#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT211_CONTROL +#define PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT212_ADDR_LO +#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT212_ADDR_HI +#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT212_MSG_DATA +#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT212_CONTROL +#define PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT213_ADDR_LO +#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT213_ADDR_HI +#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT213_MSG_DATA +#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT213_CONTROL +#define PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT214_ADDR_LO +#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT214_ADDR_HI +#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT214_MSG_DATA +#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT214_CONTROL +#define PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT215_ADDR_LO +#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT215_ADDR_HI +#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT215_MSG_DATA +#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT215_CONTROL +#define PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT216_ADDR_LO +#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT216_ADDR_HI +#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT216_MSG_DATA +#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT216_CONTROL +#define PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT217_ADDR_LO +#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT217_ADDR_HI +#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT217_MSG_DATA +#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT217_CONTROL +#define PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT218_ADDR_LO +#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT218_ADDR_HI +#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT218_MSG_DATA +#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT218_CONTROL +#define PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT219_ADDR_LO +#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT219_ADDR_HI +#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT219_MSG_DATA +#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT219_CONTROL +#define PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT220_ADDR_LO +#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT220_ADDR_HI +#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT220_MSG_DATA +#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT220_CONTROL +#define PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT221_ADDR_LO +#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT221_ADDR_HI +#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT221_MSG_DATA +#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT221_CONTROL +#define PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT222_ADDR_LO +#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT222_ADDR_HI +#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT222_MSG_DATA +#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT222_CONTROL +#define PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT223_ADDR_LO +#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT223_ADDR_HI +#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT223_MSG_DATA +#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT223_CONTROL +#define PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT224_ADDR_LO +#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT224_ADDR_HI +#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT224_MSG_DATA +#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT224_CONTROL +#define PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT225_ADDR_LO +#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT225_ADDR_HI +#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT225_MSG_DATA +#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT225_CONTROL +#define PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT226_ADDR_LO +#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT226_ADDR_HI +#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT226_MSG_DATA +#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT226_CONTROL +#define PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT227_ADDR_LO +#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT227_ADDR_HI +#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT227_MSG_DATA +#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT227_CONTROL +#define PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT228_ADDR_LO +#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT228_ADDR_HI +#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT228_MSG_DATA +#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT228_CONTROL +#define PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT229_ADDR_LO +#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT229_ADDR_HI +#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT229_MSG_DATA +#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT229_CONTROL +#define PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT230_ADDR_LO +#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT230_ADDR_HI +#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT230_MSG_DATA +#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT230_CONTROL +#define PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT231_ADDR_LO +#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT231_ADDR_HI +#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT231_MSG_DATA +#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT231_CONTROL +#define PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT232_ADDR_LO +#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT232_ADDR_HI +#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT232_MSG_DATA +#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT232_CONTROL +#define PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT233_ADDR_LO +#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT233_ADDR_HI +#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT233_MSG_DATA +#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT233_CONTROL +#define PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT234_ADDR_LO +#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT234_ADDR_HI +#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT234_MSG_DATA +#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT234_CONTROL +#define PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT235_ADDR_LO +#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT235_ADDR_HI +#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT235_MSG_DATA +#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT235_CONTROL +#define PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT236_ADDR_LO +#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT236_ADDR_HI +#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT236_MSG_DATA +#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT236_CONTROL +#define PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT237_ADDR_LO +#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT237_ADDR_HI +#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT237_MSG_DATA +#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT237_CONTROL +#define PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT238_ADDR_LO +#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT238_ADDR_HI +#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT238_MSG_DATA +#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT238_CONTROL +#define PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT239_ADDR_LO +#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT239_ADDR_HI +#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT239_MSG_DATA +#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT239_CONTROL +#define PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT240_ADDR_LO +#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT240_ADDR_HI +#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT240_MSG_DATA +#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT240_CONTROL +#define PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT241_ADDR_LO +#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT241_ADDR_HI +#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT241_MSG_DATA +#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT241_CONTROL +#define PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT242_ADDR_LO +#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT242_ADDR_HI +#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT242_MSG_DATA +#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT242_CONTROL +#define PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT243_ADDR_LO +#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT243_ADDR_HI +#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT243_MSG_DATA +#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT243_CONTROL +#define PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT244_ADDR_LO +#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT244_ADDR_HI +#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT244_MSG_DATA +#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT244_CONTROL +#define PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT245_ADDR_LO +#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT245_ADDR_HI +#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT245_MSG_DATA +#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT245_CONTROL +#define PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT246_ADDR_LO +#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT246_ADDR_HI +#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT246_MSG_DATA +#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT246_CONTROL +#define PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT247_ADDR_LO +#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT247_ADDR_HI +#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT247_MSG_DATA +#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT247_CONTROL +#define PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT248_ADDR_LO +#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT248_ADDR_HI +#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT248_MSG_DATA +#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT248_CONTROL +#define PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT249_ADDR_LO +#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT249_ADDR_HI +#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT249_MSG_DATA +#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT249_CONTROL +#define PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT250_ADDR_LO +#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT250_ADDR_HI +#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT250_MSG_DATA +#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT250_CONTROL +#define PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT251_ADDR_LO +#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT251_ADDR_HI +#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT251_MSG_DATA +#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT251_CONTROL +#define PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT252_ADDR_LO +#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT252_ADDR_HI +#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT252_MSG_DATA +#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT252_CONTROL +#define PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT253_ADDR_LO +#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT253_ADDR_HI +#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT253_MSG_DATA +#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT253_CONTROL +#define PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT254_ADDR_LO +#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT254_ADDR_HI +#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT254_MSG_DATA +#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT254_CONTROL +#define PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK 0x00000001L +//PCIEMSIX_VECT255_ADDR_LO +#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//PCIEMSIX_VECT255_ADDR_HI +#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT255_MSG_DATA +#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//PCIEMSIX_VECT255_CONTROL +#define PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT 0x0 +#define PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK 0x00000001L + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXPDEC +//PCIEMSIX_PBA_0 +#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_1 +#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_2 +#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_3 +#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_4 +#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_5 +#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_6 +#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL +//PCIEMSIX_PBA_7 +#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT 0x0 +#define PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_bif_swus_SUMDEC +//SUM_INDEX +#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +#define SUM_INDEX__SUM_INDEX_MASK 0xFFFFFFFFL +//SUM_DATA +#define SUM_DATA__SUM_DATA__SHIFT 0x0 +#define SUM_DATA__SUM_DATA_MASK 0xFFFFFFFFL +//SUM_INDEX_HI +#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT 0x0 +#define SUM_INDEX_HI__SUM_INDEX_HI_MASK 0x000000FFL + + +// addressBlock: aid_nbio_nbif0_rcc_strap_rcc_strap_internal +//RCC_STRAP1_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP1_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP1_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_DEV1_PORT_STRAP0 +//RCC_DEV1_PORT_STRAP1 +//RCC_DEV1_PORT_STRAP2 +//RCC_DEV1_PORT_STRAP3 +//RCC_DEV1_PORT_STRAP4 +//RCC_DEV1_PORT_STRAP5 +//RCC_DEV1_PORT_STRAP6 +//RCC_DEV1_PORT_STRAP7 +//RCC_DEV1_PORT_STRAP8 +//RCC_DEV1_PORT_STRAP9 +//RCC_DEV1_PORT_STRAP10 +//RCC_DEV1_PORT_STRAP11 +//RCC_DEV1_PORT_STRAP12 +//RCC_DEV1_PORT_STRAP13 +//RCC_DEV1_PORT_STRAP14 +//RCC_DEV2_PORT_STRAP0 +//RCC_DEV2_PORT_STRAP1 +//RCC_DEV2_PORT_STRAP2 +//RCC_DEV2_PORT_STRAP3 +//RCC_DEV2_PORT_STRAP4 +//RCC_DEV2_PORT_STRAP5 +//RCC_DEV2_PORT_STRAP6 +//RCC_DEV2_PORT_STRAP7 +//RCC_DEV2_PORT_STRAP8 +//RCC_DEV2_PORT_STRAP9 +//RCC_DEV2_PORT_STRAP10 +//RCC_DEV2_PORT_STRAP11 +//RCC_DEV2_PORT_STRAP12 +//RCC_DEV2_PORT_STRAP13 +//RCC_DEV2_PORT_STRAP14 +//RCC_STRAP1_RCC_BIF_STRAP0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP1 +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP2 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP1_RCC_BIF_STRAP3 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP4 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_BIF_STRAP5 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP1_RCC_BIF_STRAP6 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L + + +// addressBlock: aid_nbio_nbif0_bif_rst_bif_rst_regblk +//HARD_RST_CTRL +#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9 +#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa +#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17 +#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L +#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L +#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L +#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L +#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L +#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L +#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L +#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L +#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L +#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L +#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L +#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L +#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L +#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L +//SELF_SOFT_RST +#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19 +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a +#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b +#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L +#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L +#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L +#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L +#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L +#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L +//BIF_GFX_DRV_VPU_RST +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L +#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L +//BIF_RST_MISC_CTRL +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L +#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL +#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L +#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L +#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L +#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L +#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L +#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L +#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L +#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L +//BIF_RST_MISC_CTRL2 +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT 0x0 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT 0x1 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT 0x2 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT 0xf +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT 0x1e +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK 0x00000001L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK 0x00000002L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK 0x00000004L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK 0x00008000L +#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L +#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L +#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L +#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK 0x40000000L +#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L +//BIF_RST_MISC_CTRL3 +#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L +#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L +#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L +//DEV0_PF0_FLR_RST_CTRL +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L +#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L +#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L +#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L +//DEV0_PF1_FLR_RST_CTRL +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L +#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L +//BIF_INST_RESET_INTR_STS +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L +#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L +#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L +//BIF_PF_FLR_INTR_STS +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L +#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L +//BIF_D3HOTD0_INTR_STS +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L +//BIF_POWER_INTR_STS +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L +#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_STS +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L +//SELF_SOFT_RST_2 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0 +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1 +#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2 +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3 +#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4 +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5 +#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6 +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7 +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18 +#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19 +#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L +#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L +#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L +#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L +#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L +#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L +#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L +#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L +#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L +#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L +//BIF_INST_RESET_INTR_MASK +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L +#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L +#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L +//BIF_PF_FLR_INTR_MASK +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L +#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L +//BIF_D3HOTD0_INTR_MASK +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L +#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L +//BIF_POWER_INTR_MASK +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L +#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L +//BIF_PF_DSTATE_INTR_MASK +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L +#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L +//BIF_PF_FLR_RST +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//BIF_DEV0_PF0_DSTATE_VALUE +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L +//BIF_DEV0_PF1_DSTATE_VALUE +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L +#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L +//DEV0_PF0_D3HOTD0_RST_CTRL +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//DEV0_PF1_D3HOTD0_RST_CTRL +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L +#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L +//BIF_PORT0_DSTATE_VALUE +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L +#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L + + +// addressBlock: aid_nbio_nbif0_bif_misc_bif_misc_regblk +//REGS_ROM_OFFSET_CTRL +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT 0x0 +#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK 0x7FL +//NBIF_STRAP_BIOS_CNTL +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT 0x1 +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L +#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK 0x00000002L +//DOORBELL0_CTRL_ENTRY_0 +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_0__BIF_DOORBELL0_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_0__DOORBELL0_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_1 +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_1__BIF_DOORBELL1_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_1__DOORBELL1_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_2 +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_2__BIF_DOORBELL2_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_2__DOORBELL2_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_3 +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_3__BIF_DOORBELL3_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_3__DOORBELL3_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_4 +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_4__BIF_DOORBELL4_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_4__DOORBELL4_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_5 +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_5__BIF_DOORBELL5_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_5__DOORBELL5_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_6 +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_6__BIF_DOORBELL6_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_6__DOORBELL6_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_7 +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_7__BIF_DOORBELL7_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_7__DOORBELL7_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_8 +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_8__BIF_DOORBELL8_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_8__DOORBELL8_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_9 +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_9__BIF_DOORBELL9_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_9__DOORBELL9_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_10 +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_10__BIF_DOORBELL10_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_10__DOORBELL10_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_11 +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_11__BIF_DOORBELL11_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_11__DOORBELL11_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_12 +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_12__BIF_DOORBELL12_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_12__DOORBELL12_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_13 +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_13__BIF_DOORBELL13_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_13__DOORBELL13_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_14 +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_14__BIF_DOORBELL14_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_14__DOORBELL14_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_15 +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_15__BIF_DOORBELL15_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_15__DOORBELL15_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_16 +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_16__BIF_DOORBELL16_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_16__DOORBELL16_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_17 +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_17__BIF_DOORBELL17_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_17__DOORBELL17_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_18 +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_18__BIF_DOORBELL18_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_18__DOORBELL18_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_19 +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_19__BIF_DOORBELL19_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_19__DOORBELL19_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//DOORBELL0_CTRL_ENTRY_20 +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY__SHIFT 0x0 +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY__SHIFT 0xa +#define DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY__SHIFT 0x10 +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_OFFSET_ENTRY_MASK 0x000003FFL +#define DOORBELL0_CTRL_ENTRY_20__BIF_DOORBELL20_RANGE_SIZE_ENTRY_MASK 0x00007C00L +#define DOORBELL0_CTRL_ENTRY_20__DOORBELL20_FENCE_ENABLE_ENTRY_MASK 0x001F0000L +//AID0_VF0_BASE_ADDR +#define AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_VF0_BASE_ADDR__AID0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF0_BASE_ADDR +#define AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID1_VF0_BASE_ADDR__AID1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF0_BASE_ADDR +#define AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR__SHIFT 0x0 +#define AID2_VF0_BASE_ADDR__AID2_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF0_BASE_ADDR +#define AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR__SHIFT 0x0 +#define AID3_VF0_BASE_ADDR__AID3_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF0_BASE_ADDR +#define AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF0_BASE_ADDR__AID0_XCC0_VF0_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF0_BASE_ADDR +#define AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF0_BASE_ADDR__AID0_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF0_BASE_ADDR +#define AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF0_BASE_ADDR__AID1_XCC0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF0_BASE_ADDR +#define AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF0_BASE_ADDR__AID1_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF0_BASE_ADDR +#define AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF0_BASE_ADDR__AID2_XCC0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF0_BASE_ADDR +#define AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF0_BASE_ADDR__AID2_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF0_BASE_ADDR +#define AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF0_BASE_ADDR__AID3_XCC0_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF0_BASE_ADDR +#define AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF0_BASE_ADDR__AID3_XCC1_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF0_BASE_ADDR +#define AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF0_BASE_ADDR__AID0_NBIF_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF0_BASE_ADDR +#define AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF0_BASE_ADDR__AID0_ATHUB_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF0_BASE_ADDR +#define AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF0_BASE_ADDR__AID0_IH_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF0_BASE_ADDR +#define AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF0_BASE_ADDR__AID0_HDP_VF0_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF1_BASE_ADDR +#define AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_VF1_BASE_ADDR__AID0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF1_BASE_ADDR +#define AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID1_VF1_BASE_ADDR__AID1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF1_BASE_ADDR +#define AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR__SHIFT 0x0 +#define AID2_VF1_BASE_ADDR__AID2_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF1_BASE_ADDR +#define AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR__SHIFT 0x0 +#define AID3_VF1_BASE_ADDR__AID3_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF1_BASE_ADDR +#define AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF1_BASE_ADDR__AID0_XCC0_VF1_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF1_BASE_ADDR +#define AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF1_BASE_ADDR__AID0_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF1_BASE_ADDR +#define AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF1_BASE_ADDR__AID1_XCC0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF1_BASE_ADDR +#define AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF1_BASE_ADDR__AID1_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF1_BASE_ADDR +#define AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF1_BASE_ADDR__AID2_XCC0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF1_BASE_ADDR +#define AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF1_BASE_ADDR__AID2_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF1_BASE_ADDR +#define AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF1_BASE_ADDR__AID3_XCC0_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF1_BASE_ADDR +#define AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF1_BASE_ADDR__AID3_XCC1_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF1_BASE_ADDR +#define AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF1_BASE_ADDR__AID0_NBIF_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF1_BASE_ADDR +#define AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF1_BASE_ADDR__AID0_ATHUB_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF1_BASE_ADDR +#define AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF1_BASE_ADDR__AID0_IH_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF1_BASE_ADDR +#define AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF1_BASE_ADDR__AID0_HDP_VF1_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF2_BASE_ADDR +#define AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_VF2_BASE_ADDR__AID0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF2_BASE_ADDR +#define AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID1_VF2_BASE_ADDR__AID1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF2_BASE_ADDR +#define AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR__SHIFT 0x0 +#define AID2_VF2_BASE_ADDR__AID2_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF2_BASE_ADDR +#define AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR__SHIFT 0x0 +#define AID3_VF2_BASE_ADDR__AID3_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF2_BASE_ADDR +#define AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF2_BASE_ADDR__AID0_XCC0_VF2_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF2_BASE_ADDR +#define AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF2_BASE_ADDR__AID0_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF2_BASE_ADDR +#define AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF2_BASE_ADDR__AID1_XCC0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF2_BASE_ADDR +#define AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF2_BASE_ADDR__AID1_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF2_BASE_ADDR +#define AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF2_BASE_ADDR__AID2_XCC0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF2_BASE_ADDR +#define AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF2_BASE_ADDR__AID2_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF2_BASE_ADDR +#define AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF2_BASE_ADDR__AID3_XCC0_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF2_BASE_ADDR +#define AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF2_BASE_ADDR__AID3_XCC1_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF2_BASE_ADDR +#define AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF2_BASE_ADDR__AID0_NBIF_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF2_BASE_ADDR +#define AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF2_BASE_ADDR__AID0_ATHUB_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF2_BASE_ADDR +#define AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF2_BASE_ADDR__AID0_IH_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF2_BASE_ADDR +#define AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF2_BASE_ADDR__AID0_HDP_VF2_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF3_BASE_ADDR +#define AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_VF3_BASE_ADDR__AID0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF3_BASE_ADDR +#define AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID1_VF3_BASE_ADDR__AID1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF3_BASE_ADDR +#define AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR__SHIFT 0x0 +#define AID2_VF3_BASE_ADDR__AID2_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF3_BASE_ADDR +#define AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR__SHIFT 0x0 +#define AID3_VF3_BASE_ADDR__AID3_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF3_BASE_ADDR +#define AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF3_BASE_ADDR__AID0_XCC0_VF3_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF3_BASE_ADDR +#define AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF3_BASE_ADDR__AID0_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF3_BASE_ADDR +#define AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF3_BASE_ADDR__AID1_XCC0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF3_BASE_ADDR +#define AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF3_BASE_ADDR__AID1_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF3_BASE_ADDR +#define AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF3_BASE_ADDR__AID2_XCC0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF3_BASE_ADDR +#define AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF3_BASE_ADDR__AID2_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF3_BASE_ADDR +#define AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF3_BASE_ADDR__AID3_XCC0_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF3_BASE_ADDR +#define AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF3_BASE_ADDR__AID3_XCC1_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF3_BASE_ADDR +#define AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF3_BASE_ADDR__AID0_NBIF_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF3_BASE_ADDR +#define AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF3_BASE_ADDR__AID0_ATHUB_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF3_BASE_ADDR +#define AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF3_BASE_ADDR__AID0_IH_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF3_BASE_ADDR +#define AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF3_BASE_ADDR__AID0_HDP_VF3_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF4_BASE_ADDR +#define AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_VF4_BASE_ADDR__AID0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF4_BASE_ADDR +#define AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID1_VF4_BASE_ADDR__AID1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF4_BASE_ADDR +#define AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR__SHIFT 0x0 +#define AID2_VF4_BASE_ADDR__AID2_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF4_BASE_ADDR +#define AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR__SHIFT 0x0 +#define AID3_VF4_BASE_ADDR__AID3_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF4_BASE_ADDR +#define AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF4_BASE_ADDR__AID0_XCC0_VF4_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF4_BASE_ADDR +#define AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF4_BASE_ADDR__AID0_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF4_BASE_ADDR +#define AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF4_BASE_ADDR__AID1_XCC0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF4_BASE_ADDR +#define AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF4_BASE_ADDR__AID1_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF4_BASE_ADDR +#define AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF4_BASE_ADDR__AID2_XCC0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF4_BASE_ADDR +#define AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF4_BASE_ADDR__AID2_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF4_BASE_ADDR +#define AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF4_BASE_ADDR__AID3_XCC0_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF4_BASE_ADDR +#define AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF4_BASE_ADDR__AID3_XCC1_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF4_BASE_ADDR +#define AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF4_BASE_ADDR__AID0_NBIF_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF4_BASE_ADDR +#define AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF4_BASE_ADDR__AID0_ATHUB_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF4_BASE_ADDR +#define AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF4_BASE_ADDR__AID0_IH_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF4_BASE_ADDR +#define AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF4_BASE_ADDR__AID0_HDP_VF4_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF5_BASE_ADDR +#define AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_VF5_BASE_ADDR__AID0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF5_BASE_ADDR +#define AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID1_VF5_BASE_ADDR__AID1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF5_BASE_ADDR +#define AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR__SHIFT 0x0 +#define AID2_VF5_BASE_ADDR__AID2_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF5_BASE_ADDR +#define AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR__SHIFT 0x0 +#define AID3_VF5_BASE_ADDR__AID3_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF5_BASE_ADDR +#define AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF5_BASE_ADDR__AID0_XCC0_VF5_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF5_BASE_ADDR +#define AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF5_BASE_ADDR__AID0_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF5_BASE_ADDR +#define AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF5_BASE_ADDR__AID1_XCC0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF5_BASE_ADDR +#define AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF5_BASE_ADDR__AID1_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF5_BASE_ADDR +#define AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF5_BASE_ADDR__AID2_XCC0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF5_BASE_ADDR +#define AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF5_BASE_ADDR__AID2_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF5_BASE_ADDR +#define AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF5_BASE_ADDR__AID3_XCC0_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF5_BASE_ADDR +#define AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF5_BASE_ADDR__AID3_XCC1_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF5_BASE_ADDR +#define AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF5_BASE_ADDR__AID0_NBIF_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF5_BASE_ADDR +#define AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF5_BASE_ADDR__AID0_ATHUB_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF5_BASE_ADDR +#define AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF5_BASE_ADDR__AID0_IH_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF5_BASE_ADDR +#define AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF5_BASE_ADDR__AID0_HDP_VF5_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF6_BASE_ADDR +#define AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_VF6_BASE_ADDR__AID0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF6_BASE_ADDR +#define AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID1_VF6_BASE_ADDR__AID1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF6_BASE_ADDR +#define AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR__SHIFT 0x0 +#define AID2_VF6_BASE_ADDR__AID2_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF6_BASE_ADDR +#define AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR__SHIFT 0x0 +#define AID3_VF6_BASE_ADDR__AID3_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF6_BASE_ADDR +#define AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF6_BASE_ADDR__AID0_XCC0_VF6_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF6_BASE_ADDR +#define AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF6_BASE_ADDR__AID0_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF6_BASE_ADDR +#define AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF6_BASE_ADDR__AID1_XCC0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF6_BASE_ADDR +#define AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF6_BASE_ADDR__AID1_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF6_BASE_ADDR +#define AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF6_BASE_ADDR__AID2_XCC0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF6_BASE_ADDR +#define AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF6_BASE_ADDR__AID2_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF6_BASE_ADDR +#define AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF6_BASE_ADDR__AID3_XCC0_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF6_BASE_ADDR +#define AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF6_BASE_ADDR__AID3_XCC1_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF6_BASE_ADDR +#define AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF6_BASE_ADDR__AID0_NBIF_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF6_BASE_ADDR +#define AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF6_BASE_ADDR__AID0_ATHUB_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF6_BASE_ADDR +#define AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF6_BASE_ADDR__AID0_IH_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF6_BASE_ADDR +#define AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF6_BASE_ADDR__AID0_HDP_VF6_BASE_ADDR_MASK 0x0000FFFFL +//AID0_VF7_BASE_ADDR +#define AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_VF7_BASE_ADDR__AID0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID1_VF7_BASE_ADDR +#define AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID1_VF7_BASE_ADDR__AID1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID2_VF7_BASE_ADDR +#define AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR__SHIFT 0x0 +#define AID2_VF7_BASE_ADDR__AID2_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID3_VF7_BASE_ADDR +#define AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR__SHIFT 0x0 +#define AID3_VF7_BASE_ADDR__AID3_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_VF7_BASE_ADDR +#define AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_VF7_BASE_ADDR__AID0_XCC0_VF7_BASE_ADDR_MASK 0x0001FFFFL +//AID0_XCC1_VF7_BASE_ADDR +#define AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_VF7_BASE_ADDR__AID0_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_VF7_BASE_ADDR +#define AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_VF7_BASE_ADDR__AID1_XCC0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_VF7_BASE_ADDR +#define AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_VF7_BASE_ADDR__AID1_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_VF7_BASE_ADDR +#define AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_VF7_BASE_ADDR__AID2_XCC0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_VF7_BASE_ADDR +#define AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_VF7_BASE_ADDR__AID2_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_VF7_BASE_ADDR +#define AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_VF7_BASE_ADDR__AID3_XCC0_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_VF7_BASE_ADDR +#define AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_VF7_BASE_ADDR__AID3_XCC1_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_NBIF_VF7_BASE_ADDR +#define AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_NBIF_VF7_BASE_ADDR__AID0_NBIF_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_ATHUB_VF7_BASE_ADDR +#define AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_ATHUB_VF7_BASE_ADDR__AID0_ATHUB_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_IH_VF7_BASE_ADDR +#define AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_IH_VF7_BASE_ADDR__AID0_IH_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_HDP_VF7_BASE_ADDR +#define AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR__SHIFT 0x0 +#define AID0_HDP_VF7_BASE_ADDR__AID0_HDP_VF7_BASE_ADDR_MASK 0x0000FFFFL +//AID0_PF_BASE_ADDR +#define AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR__SHIFT 0x0 +#define AID0_PF_BASE_ADDR__AID0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC0_PF_BASE_ADDR +#define AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC0_PF_BASE_ADDR__AID0_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID0_XCC1_PF_BASE_ADDR +#define AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID0_XCC1_PF_BASE_ADDR__AID0_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID1_PF_BASE_ADDR +#define AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR__SHIFT 0x0 +#define AID1_PF_BASE_ADDR__AID1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC0_PF_BASE_ADDR +#define AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC0_PF_BASE_ADDR__AID1_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID1_XCC1_PF_BASE_ADDR +#define AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID1_XCC1_PF_BASE_ADDR__AID1_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID2_PF_BASE_ADDR +#define AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR__SHIFT 0x0 +#define AID2_PF_BASE_ADDR__AID2_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC0_PF_BASE_ADDR +#define AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC0_PF_BASE_ADDR__AID2_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID2_XCC1_PF_BASE_ADDR +#define AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID2_XCC1_PF_BASE_ADDR__AID2_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID3_PF_BASE_ADDR +#define AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR__SHIFT 0x0 +#define AID3_PF_BASE_ADDR__AID3_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC0_PF_BASE_ADDR +#define AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC0_PF_BASE_ADDR__AID3_XCC0_PF_BASE_ADDR_MASK 0x0000FFFFL +//AID3_XCC1_PF_BASE_ADDR +#define AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR__SHIFT 0x0 +#define AID3_XCC1_PF_BASE_ADDR__AID3_XCC1_PF_BASE_ADDR_MASK 0x0000FFFFL +//NBIF_RRMT_CNTL +#define NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT 0x0 +#define NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT 0x4 +#define NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT 0x8 +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT 0x18 +#define NBIF_RRMT_CNTL__PARTITION_MODE_MASK 0x00000007L +#define NBIF_RRMT_CNTL__AID_DIE_ID_MASK 0x00000030L +#define NBIF_RRMT_CNTL__RRMT_ENABLE_MASK 0x00000100L +#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK 0xFF000000L +//BIFC_DOORBELL_ACCESS_EN_PF +#define BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_PF__BIFC_DOORBELL_ACCESS_EN_PF_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF0 +#define BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF0__BIFC_DOORBELL_ACCESS_EN_VF0_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF1 +#define BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF1__BIFC_DOORBELL_ACCESS_EN_VF1_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF2 +#define BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF2__BIFC_DOORBELL_ACCESS_EN_VF2_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF3 +#define BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF3__BIFC_DOORBELL_ACCESS_EN_VF3_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF4 +#define BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF4__BIFC_DOORBELL_ACCESS_EN_VF4_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF5 +#define BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF5__BIFC_DOORBELL_ACCESS_EN_VF5_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF6 +#define BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF6__BIFC_DOORBELL_ACCESS_EN_VF6_MASK 0x000FFFFFL +//BIFC_DOORBELL_ACCESS_EN_VF7 +#define BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7__SHIFT 0x0 +#define BIFC_DOORBELL_ACCESS_EN_VF7__BIFC_DOORBELL_ACCESS_EN_VF7_MASK 0x000FFFFFL +//MISC_SCRATCH +#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL +//INTR_LINE_POLARITY +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL +//INTR_LINE_ENABLE +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL +//OUTSTANDING_VC_ALLOC +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L +#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L +#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L +//BIFC_MISC_CTRL0 +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4 +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT 0x9 +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT 0xe +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT 0xf +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12 +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13 +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14 +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT 0x15 +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT 0x16 +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT 0x17 +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT 0x19 +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT 0x1d +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT 0x1e +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK 0x00000001L +#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK 0x00000006L +#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L +#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK 0x00000200L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L +#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L +#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L +#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK 0x00004000L +#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK 0x00008000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L +#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L +#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L +#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L +#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK 0x00200000L +#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK 0x00400000L +#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK 0x00800000L +#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L +#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK 0x02000000L +#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L +#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L +#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L +#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK 0x20000000L +#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK 0x40000000L +#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L +//BIFC_MISC_CTRL1 +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT 0x15 +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT 0x16 +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17 +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18 +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19 +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e +#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L +#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L +#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L +#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L +#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L +#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L +#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L +#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L +#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L +#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L +#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L +#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L +#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L +#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK 0x00200000L +#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK 0x00400000L +#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L +#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L +#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L +#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L +#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L +#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L +#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L +//BIFC_BME_ERR_LOG_LB +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_LC_TIMER_CTRL +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0 +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10 +#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL +#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L +//BIFC_RCCBIH_BME_ERR_LOG0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L +#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L +#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L +//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L +#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L +//BIFC_DMA_ATTR_CNTL2_DEV0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18 +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L +#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L +//BME_DUMMY_CNTL_0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L +#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L +//BIFC_THT_CNTL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x10 +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT 0x18 +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x19 +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT 0x1a +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT 0x1b +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK 0x0000000FL +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK 0x000000F0L +#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK 0x00000F00L +#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK 0x00010000L +#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK 0x01000000L +#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK 0x02000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK 0x04000000L +#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK 0x08000000L +//BIFC_HSTARB_CNTL +#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8 +#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L +#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L +//BIFC_GSI_CNTL +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0xf +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x10 +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x11 +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f +#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L +#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL +#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L +#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L +#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L +#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L +#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L +#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00008000L +#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00010000L +#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00020000L +#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L +#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L +//BIFC_PCIEFUNC_CNTL +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL +//BIFC_PASID_CHECK_DIS +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1 +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L +#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L +//BIFC_SDP_CNTL_0 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8 +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10 +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18 +#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L +#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L +#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L +//BIFC_SDP_CNTL_1 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1 +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4 +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5 +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7 +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8 +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT 0x9 +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L +#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L +#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L +#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L +#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L +#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L +#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L +#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK 0x00000200L +//BIFC_PASID_STS +#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0 +#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL +//BIFC_ATHUB_ACT_CNTL +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT 0x3 +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8 +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0x9 +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT 0xa +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK 0x00000038L +#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L +#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000200L +#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK 0x00000400L +//BIFC_PERF_CNTL_0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L +#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L +//BIFC_PERF_CNTL_1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x4 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x5 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x8 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x10 +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000010L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000020L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x0000FF00L +#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0x01FF0000L +//BIFC_PERF_CNT_MMIO_RD_L32BIT +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_MMIO_WR_L32BIT +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_RD_L32BIT +#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK 0xFFFFFFFFL +//BIFC_PERF_CNT_DMA_WR_L32BIT +#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK 0xFFFFFFFFL +//NBIF_REGIF_ERRSET_CTRL +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +//BIFC_SDP_CNTL_2 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10 +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18 +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L +#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L +//NBIF_PGMST_CTRL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8 +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L +#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//NBIF_PGSLV_CTRL +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL +//NBIF_PG_MISC_CTRL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10 +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L +#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//SMN_MST_EP_CNTL3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_CNTL1 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L +#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L +//SMN_MST_EP_CNTL5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L +//BIF_SELFRING_BUFFER_VID +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8 +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10 +#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL +#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L +#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L +//BIF_SELFRING_VECTOR_CNTL +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1 +#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L +#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L +//NBIF_STRAP_WRITE_CTRL +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 +#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L +//NBIF_INTX_DSTATE_MISC_CNTL +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6 +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7 +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L +#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L +#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L +//NBIF_PENDING_MISC_CNTL +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0 +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1 +#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L +#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L +//BIF_GMI_WRR_WEIGHT +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L +#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L +//BIF_GMI_WRR_WEIGHT2 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L +//BIF_GMI_WRR_WEIGHT3 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18 +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L +#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L +//NBIF_PWRBRK_REQUEST +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0 +#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L +//BIF_ATOMIC_ERR_LOG_DEV0_F0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L +//BIF_ATOMIC_ERR_LOG_DEV0_F1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13 +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L +#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L +//BIF_DMA_MP4_ERR_LOG +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10 +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11 +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L +#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L +#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L +//BIF_PASID_ERR_LOG +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L +//BIF_PASID_ERR_CLR +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1 +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L +#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L +//NBIF_VWIRE_CTRL +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0 +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10 +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L +#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L +#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L +#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L +#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L +#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L +//NBIF_SMN_VWR_VCHG_DIS_CTRL +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L +//NBIF_SMN_VWR_VCHG_RST_CTRL0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L +//NBIF_SMN_VWR_VCHG_TRIG +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L +//NBIF_SMN_VWR_WTRIG_CNTL +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L +#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L +//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L +#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L +//NBIF_MGCG_CTRL_LCLK +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2 +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT 0xe +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L +#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK 0x00004000L +//NBIF_DS_CTRL_LCLK +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L +#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK 0x00000002L +#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L +//SMN_MST_CNTL0 +#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L +#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L +#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L +#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L +#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L +//SMN_MST_EP_CNTL1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L +//SMN_MST_EP_CNTL2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L +#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L +//NBIF_SDP_VWR_VCHG_DIS_CTRL +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_RST_CTRL1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L +//NBIF_SDP_VWR_VCHG_TRIG +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L +#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L +//NBIF_SHUB_TODET_CTRL +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10 +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L +#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L +//NBIF_SHUB_TODET_CLIENT_CTRL +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_CTRL2 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_CLIENT_STATUS2 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT 0x0 +#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK 0xFFFFFFFFL +//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT 0x0 +#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK 0xFFFFFFFFL +//BIFC_BME_ERR_LOG_HB +//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18 +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L +#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L +//DISCON_HYSTERESIS_HEAD_CTRL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL +#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +//BIFC_EARLY_WAKEUP_CNTL +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//BIFC_PERF_CNT_MMIO_RD_H16BIT +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_MMIO_WR_H16BIT +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_DMA_RD_H16BIT +#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_PERF_CNT_DMA_WR_H16BIT +#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT 0x0 +#define BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK 0x0000FFFFL +//BIFC_A2S_SDP_PORT_CTRL +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x8 +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT 0xc +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L +#define BIFC_A2S_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK 0x00001000L +//BIFC_A2S_CNTL_SW0 +#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP__SHIFT 0x0 +#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE__SHIFT 0x2 +#define BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x5 +#define BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x6 +#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define BIFC_A2S_CNTL_SW0__RDRSP_ERRMAP_MASK 0x00000003L +#define BIFC_A2S_CNTL_SW0__RDRSP_SEL_MODE_MASK 0x0000001CL +#define BIFC_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000020L +#define BIFC_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x000001C0L +#define BIFC_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define BIFC_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define BIFC_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define BIFC_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define BIFC_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//BIFC_A2S_MISC_CNTL +#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +#define BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3 +#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 +#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 +#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 +#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 +#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 +#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa +#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 +#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 +#define BIFC_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a +#define BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN__SHIFT 0x1c +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE__SHIFT 0x1d +#define BIFC_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define BIFC_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L +#define BIFC_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L +#define BIFC_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L +#define BIFC_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L +#define BIFC_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +#define BIFC_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L +#define BIFC_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L +#define BIFC_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L +#define BIFC_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L +#define BIFC_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L +#define BIFC_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L +#define BIFC_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L +#define BIFC_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_EN_MASK 0x10000000L +#define BIFC_A2S_MISC_CNTL__BYPASS_OVERRIDE_VALUE_MASK 0x20000000L +//BIFC_A2S_TAG_ALLOC_0 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define BIFC_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//BIFC_A2S_TAG_ALLOC_1 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define BIFC_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//BIFC_A2S_CNTL_CL0 +#define BIFC_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +#define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define BIFC_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +#define BIFC_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +#define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +#define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +#define BIFC_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +#define BIFC_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +#define BIFC_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L +#define BIFC_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define BIFC_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define BIFC_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define BIFC_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L +#define BIFC_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L +#define BIFC_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L +#define BIFC_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L +#define BIFC_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L +#define BIFC_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +//RCC_DWN_DEV0_2_DN_PCIE_RESERVED +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_DWN_DEV0_2_DN_PCIE_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L +//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L +//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L +//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT 0x12 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT 0x13 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK 0x00040000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK 0x00080000L +#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK 0x00100000L +//RCC_DWNP_DEV0_2_PCIE_RX_CNTL +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L +#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L +//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L +#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L +//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L +//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +//RCC_EP_DEV0_2_EP_PCIE_SCRATCH +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L +//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L +//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L +//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L +//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L +#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L +//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL +#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL +//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL +//RCC_EP_DEV0_2_EP_PCIEP_RESERVED +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL +//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L +#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L +//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L +#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L +//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L +#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L +//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT 0x3 +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L +#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK 0x00000008L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +//RCC_DEV0_1_RCC_ERR_INT_CNTL +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_BACO_CNTL_MISC +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L +#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L +//RCC_DEV0_1_RCC_RESET_EN +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L +//RCC_DEV0_2_RCC_VDM_SUPPORT +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L +#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L +//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11 +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L +#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L +//RCC_DEV0_1_RCC_GPUIOV_REGION +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4 +#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x0000000FL +#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x000000F0L +//RCC_DEV0_1_RCC_GPU_HOSTVM_EN +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L +//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL +//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL +//RCC_DEV0_1_RCC_PEER_REG_RANGE0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_1_RCC_PEER_REG_RANGE1 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL +#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_BUS_CNTL +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L +#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L +#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L +#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L +#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L +#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L +//RCC_DEV0_1_RCC_CONFIG_CNTL +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L +#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L +//RCC_DEV0_1_RCC_CONFIG_F0_BASE +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL +//RCC_DEV0_1_RCC_XDMA_LO +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL +#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_XDMA_HI +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL +//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13 +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK 0x00008000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L +#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL1 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL +//RCC_DEV0_1_RCC_BUSNUM_LIST0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_LIST1 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L +//RCC_DEV0_1_RCC_BUSNUM_CNTL2 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L +#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L +//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L +//RCC_DEV0_1_RCC_HOST_BUSNUM +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL +//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL +#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L +//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L +#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L +//RCC_DEV0_2_RCC_DEV0_LINK_CNTL +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT 0x10 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT 0x11 +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK 0x00010000L +#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK 0x00020000L +//RCC_DEV0_2_RCC_CMN_LINK_CNTL +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10 +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L +#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L +//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL +#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L +//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL +//RCC_DEV0_2_RCC_MH_ARB_CNTL +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L +#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +//BIF_BX1_PCIE_INDEX +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA +#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX2 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_DATA2 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL +//BIF_BX1_PCIE_INDEX_HI +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK 0x000000FFL +//BIF_BX1_PCIE_INDEX2_HI +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT 0x0 +#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK 0x000000FFL +//BIF_BX1_SBIOS_SCRATCH_0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_1 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_2 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_3 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_1 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_2 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_3 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_4 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_5 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_6 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_7 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_8 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_9 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_10 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_11 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_12 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_13 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_14 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_BIOS_SCRATCH_15 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RLC_INTR_CNTL +//BIF_BX1_BIF_VCE_INTR_CNTL +//BIF_BX1_BIF_UVD_INTR_CNTL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_CNTL +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL +//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_1 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_2 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_3 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_4 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_5 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_6 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_7 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_8 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_9 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_10 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_11 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_12 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_13 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_14 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_DRIVER_SCRATCH_15 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_1 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_2 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_3 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_4 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_5 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_6 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_7 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_8 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_9 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_10 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_11 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_12 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_13 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_14 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_FW_SCRATCH_15 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_4 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_5 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_6 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_7 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_8 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_9 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_10 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_11 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_12 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_13 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_14 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK 0xFFFFFFFFL +//BIF_BX1_SBIOS_SCRATCH_15 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT 0x0 +#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +//BIF_BX_PF1_MM_INDEX +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_PF1_MM_DATA +#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MM_INDEX_HI +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +//BIF_BX1_CC_BIF_BX_STRAP0 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19 +#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L +//BIF_BX1_CC_BIF_BX_PINSTRAP0 +//BIF_BX1_BIF_MM_INDACCESS_CNTL +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L +//BIF_BX1_BUS_CNTL +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa +#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19 +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f +#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L +#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L +#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L +#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L +#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L +#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L +#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L +#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L +#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L +#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L +#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L +//BIF_BX1_BIF_SCRATCH0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_SCRATCH1 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL +//BIF_BX1_BX_RESET_EN +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L +//BIF_BX1_MM_CFGREGS_CNTL +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L +#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L +//BIF_BX1_BX_RESET_CNTL +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L +//BIF_BX1_INTERRUPT_CNTL +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10 +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11 +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12 +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L +#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L +#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L +#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L +#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK 0x00000100L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L +#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L +#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L +#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L +//BIF_BX1_INTERRUPT_CNTL2 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_CLKREQB_PAD_CNTL +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L +#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L +//BIF_BX1_BIF_FEATURES_CONTROL_MISC +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT 0xe +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x19 +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK 0x00004000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x01FF0000L +#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x02000000L +//BIF_BX1_HDP_ATOMIC_CONTROL_MISC +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT 0x0 +#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK 0x000000FFL +//BIF_BX1_BIF_DOORBELL_CNTL +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L +#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L +//BIF_BX1_BIF_DOORBELL_INT_CNTL +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x17 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19 +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT 0x1f +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x00800000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L +#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK 0x80000000L +//BIF_BX1_BIF_FB_EN +#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L +#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L +//BIF_BX1_BIF_INTR_CNTL +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0 +#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L +//BIF_BX1_BIF_MST_TRANS_PENDING_VF +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_SLV_TRANS_PENDING_VF +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL +//BIF_BX1_BACO_CNTL +#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT 0x0 +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT 0x8 +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT 0x10 +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +#define BIF_BX1_BACO_CNTL__BACO_EN_MASK 0x00000001L +#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L +#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L +#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L +#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L +#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK 0x00000100L +#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L +#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK 0x00010000L +#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIME0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER1 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18 +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L +#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L +//BIF_BX1_BIF_BACO_EXIT_TIMER2 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER3 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_BIF_BACO_EXIT_TIMER4 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL +//BIF_BX1_MEM_TYPE_CNTL +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L +//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L +#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L +//BIF_BX1_NBIF_GFX_ADDR_LUT_0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_1 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_2 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_3 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_4 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_5 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_6 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_7 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_8 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_9 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_10 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_11 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_12 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_13 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_14 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_NBIF_GFX_ADDR_LUT_15 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0 +#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL +//BIF_BX1_VF_REGWR_EN +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_EN +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L +#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L +//BIF_BX1_VF_FB_EN +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L +//BIF_BX1_VF_REGWR_STATUS +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_DOORBELL_STATUS +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_VF_FB_STATUS +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19 +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L +#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L +//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL +//BIF_BX1_BIF_RB_CNTL +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT 0x19 +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L +#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L +#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK 0x02000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L +#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L +#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L +#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//BIF_BX1_BIF_RB_BASE +#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//BIF_BX1_BIF_RB_RPTR +#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L +#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL +//BIF_BX1_BIF_RB_WPTR_ADDR_HI +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL +//BIF_BX1_BIF_RB_WPTR_ADDR_LO +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//BIF_BX1_MAILBOX_INDEX +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL +//BIF_BX1_BIF_MP1_INTR_CTRL +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT 0x0 +#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK 0x00000001L +//BIF_BX1_BIF_PERSTB_PAD_CNTL +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL +//BIF_BX1_BIF_PX_EN_PAD_CNTL +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x00000FFFL +//BIF_BX1_BIF_REFPADKIN_PAD_CNTL +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_CLKREQB_PAD_CNTL +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x7FFFFFFFL +//BIF_BX1_BIF_PWRBRK_PAD_CNTL +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0 +#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL +//BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK 0x0000000FL +//BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE +#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT 0x0 +#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK 0x0000000FL + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +//BIF_BX_PF1_BIF_BME_STATUS +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_PF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_PF1_BIF_TRANS_PENDING +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_PF1_MAILBOX_CONTROL +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_PF1_MAILBOX_INT_CNTL +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_PF1_BIF_VMHV_MAILBOX +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L +//BIF_BX_PF1_PARTITION_COMPUTE_CAP +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT 0xa +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK 0x00000010L +#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK 0x0003FC00L +//BIF_BX_PF1_PARTITION_MEM_CAP +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT 0x1 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT 0x2 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT 0x3 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT 0x5 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT 0x7 +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK 0x00000001L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK 0x00000002L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK 0x00000004L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK 0x00000008L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK 0x00000020L +#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK 0x00000080L +//BIF_BX_PF1_PARTITION_COMPUTE_STATUS +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK 0x000000F0L +//BIF_BX_PF1_PARTITION_MEM_STATUS +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE__SHIFT 0x0 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT 0x4 +#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUE_MASK 0x0000000FL +#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK 0x00000FF0L + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1:1 +//RCC_STRAP2_RCC_BIF_STRAP0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK 0x000C0000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK 0x10000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP1 +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT 0x1e +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK 0x00000004L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK 0x02000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK 0x40000000L +#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP2 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN__SHIFT 0x7 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SEC_LVL_OVRD_EN_MASK 0x00000080L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L +#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L +//RCC_STRAP2_RCC_BIF_STRAP3 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP4 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_BIF_STRAP5 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT 0x15 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19 +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK 0x00200000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L +#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L +//RCC_STRAP2_RCC_BIF_STRAP6 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT 0x0 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT 0x1 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT 0x2 +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK 0x00000001L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK 0x00000002L +#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK 0x00000004L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK 0x0007FFC0L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK 0x0FFF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK 0x00FFFFFFL +//RCC_STRAP2_RCC_DEV0_PORT_STRAP13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK 0x000FFE00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK 0xFFF00000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK 0x00000010L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x2 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK 0x00000004L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0xF0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP7 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_PORT_STRAP9 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0xFF000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT 0x19 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK 0x00FFF000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK 0x3E000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK 0x00FFF000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT 0xc +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK 0x00000FFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK 0x00001000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK 0x01FFE000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP26 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP26__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK 0x00000FFFL +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT 0xa +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK 0x00000400L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L +//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L +#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP22 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP23 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP24 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP25 +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x10 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x11 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00010000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00020000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT 0x1b +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK 0x38000000L +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L +//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7 + + +// addressBlock: aid_nbio_nbif0_gdc_hst_sion_SIONDEC +//S2A_DOORBELL_ENTRY_0_CTRL +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_1_CTRL +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_2_CTRL +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_3_CTRL +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_4_CTRL +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_5_CTRL +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_6_CTRL +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_7_CTRL +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_8_CTRL +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_9_CTRL +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_10_CTRL +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_11_CTRL +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_12_CTRL +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_13_CTRL +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_14_CTRL +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_ENTRY_15_CTRL +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT 0x0 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT 0x1 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT 0x6 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT 0x7 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT 0x11 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT 0x19 +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT 0x1a +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT 0x1c +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK 0x00000001L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK 0x0000003EL +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK 0x00000040L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK 0x0001FF80L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK 0x01FE0000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK 0x02000000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK 0x04000000L +#define S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK 0xF0000000L +//S2A_DOORBELL_COMMON_CTRL_REG +#define S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x0 +#define S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00000001L + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +//GDC1_A2S_CNTL_CL0 +#define GDC1_A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +#define GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC1_A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +#define GDC1_A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +#define GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC1_A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +#define GDC1_A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +#define GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC1_A2S_CNTL_CL0__NSNOOP_MAP_MASK 0x00000003L +#define GDC1_A2S_CNTL_CL0__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC1_A2S_CNTL_CL0__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC1_A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC1_A2S_CNTL_CL0__BLKLVL_MAP_MASK 0x00000C00L +#define GDC1_A2S_CNTL_CL0__DATERR_MAP_MASK 0x00003000L +#define GDC1_A2S_CNTL_CL0__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC1_A2S_CNTL_CL0__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC1_A2S_CNTL_CL0__RESP_WR_MAP_MASK 0x000C0000L +#define GDC1_A2S_CNTL_CL0__RESP_RD_MAP_MASK 0x00300000L +#define GDC1_A2S_CNTL_CL0__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC1_A2S_CNTL_CL0__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC1_A2S_CNTL_CL0__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC1_A2S_CNTL_CL0__STATIC_VC_VALUE_MASK 0x70000000L +//GDC1_A2S_CNTL_CL1 +#define GDC1_A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 +#define GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 +#define GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +#define GDC1_A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa +#define GDC1_A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc +#define GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe +#define GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 +#define GDC1_A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 +#define GDC1_A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 +#define GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP__SHIFT 0x16 +#define GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE__SHIFT 0x18 +#define GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE__SHIFT 0x1b +#define GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE__SHIFT 0x1c +#define GDC1_A2S_CNTL_CL1__NSNOOP_MAP_MASK 0x00000003L +#define GDC1_A2S_CNTL_CL1__REQPASSPW_VC0_MAP_MASK 0x0000000CL +#define GDC1_A2S_CNTL_CL1__REQPASSPW_NVC0_MAP_MASK 0x00000030L +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP_MASK 0x000000C0L +#define GDC1_A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP_MASK 0x00000300L +#define GDC1_A2S_CNTL_CL1__BLKLVL_MAP_MASK 0x00000C00L +#define GDC1_A2S_CNTL_CL1__DATERR_MAP_MASK 0x00003000L +#define GDC1_A2S_CNTL_CL1__EXOKAY_WR_MAP_MASK 0x0000C000L +#define GDC1_A2S_CNTL_CL1__EXOKAY_RD_MAP_MASK 0x00030000L +#define GDC1_A2S_CNTL_CL1__RESP_WR_MAP_MASK 0x000C0000L +#define GDC1_A2S_CNTL_CL1__RESP_RD_MAP_MASK 0x00300000L +#define GDC1_A2S_CNTL_CL1__RDRSP_ERRMAP_MASK 0x00C00000L +#define GDC1_A2S_CNTL_CL1__RDRSP_SEL_MODE_MASK 0x07000000L +#define GDC1_A2S_CNTL_CL1__STATIC_VC_ENABLE_MASK 0x08000000L +#define GDC1_A2S_CNTL_CL1__STATIC_VC_VALUE_MASK 0x70000000L +//GDC1_A2S_CNTL3_CL0 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_PH__SHIFT 0x0 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_PH_MASK 0x00000003L +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC1_A2S_CNTL3_CL0__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC1_A2S_CNTL3_CL0__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC1_A2S_CNTL3_CL1 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_PH__SHIFT 0x0 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING__SHIFT 0x2 +#define GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE__SHIFT 0x3 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY__SHIFT 0x4 +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_PH_MASK 0x00000003L +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_STEERING_MASK 0x00000004L +#define GDC1_A2S_CNTL3_CL1__WR_ST_TAG_MODE_MASK 0x00000008L +#define GDC1_A2S_CNTL3_CL1__FORCE_WR_ST_ENTRY_MASK 0x000003F0L +//GDC1_A2S_CNTL_SW0 +#define GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC1_A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC1_A2S_CNTL_SW0__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC1_A2S_CNTL_SW0__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC1_A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC1_A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC1_A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC1_A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC1_A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC1_A2S_CNTL_SW1 +#define GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC1_A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC1_A2S_CNTL_SW1__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC1_A2S_CNTL_SW1__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC1_A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC1_A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC1_A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC1_A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC1_A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC1_A2S_CNTL_SW2 +#define GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT 0x0 +#define GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT 0x1 +#define GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 +#define GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT 0xa +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT 0xb +#define GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT 0xc +#define GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +#define GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +#define GDC1_A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK 0x00000001L +#define GDC1_A2S_CNTL_SW2__STATIC_VC_VALUE_MASK 0x0000000EL +#define GDC1_A2S_CNTL_SW2__FORCE_RSP_REORDER_EN_MASK 0x00000040L +#define GDC1_A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK 0x00000200L +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK 0x00000400L +#define GDC1_A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK 0x00000800L +#define GDC1_A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK 0x00001000L +#define GDC1_A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK 0x00FF0000L +#define GDC1_A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK 0xFF000000L +//GDC1_A2S_TAG_ALLOC_0 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT 0x0 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT 0x8 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT 0x10 +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK 0x000000FFL +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK 0x0000FF00L +#define GDC1_A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK 0x00FF0000L +//GDC1_A2S_TAG_ALLOC_1 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT 0x0 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT 0x10 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT 0x18 +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK 0x000000FFL +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK 0x00FF0000L +#define GDC1_A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK 0xFF000000L +//GDC1_A2S_MISC_CNTL +#define GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +#define GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +#define GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE__SHIFT 0x3 +#define GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN__SHIFT 0x4 +#define GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS__SHIFT 0x5 +#define GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT 0x6 +#define GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x7 +#define GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0x8 +#define GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0x9 +#define GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0xa +#define GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN__SHIFT 0x10 +#define GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN__SHIFT 0x15 +#define GDC1_A2S_MISC_CNTL__WRR_LRG_MODE__SHIFT 0x1a +#define GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE__SHIFT 0x1b +#define GDC1_A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK 0x00000003L +#define GDC1_A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS_MASK 0x00000004L +#define GDC1_A2S_MISC_CNTL__WRR_LRG_SIZE_MODE_MASK 0x00000008L +#define GDC1_A2S_MISC_CNTL__FORCE_RSP_REORDER_EN_MASK 0x00000010L +#define GDC1_A2S_MISC_CNTL__RSP_REORDER_DIS_MASK 0x00000020L +#define GDC1_A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK 0x00000040L +#define GDC1_A2S_MISC_CNTL__WRRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000080L +#define GDC1_A2S_MISC_CNTL__RDRSP_TAGFIFO_CONT_RD_DIS_MASK 0x00000100L +#define GDC1_A2S_MISC_CNTL__RDRSP_STS_DATSTS_PRIORITY_MASK 0x00000200L +#define GDC1_A2S_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000400L +#define GDC1_A2S_MISC_CNTL__WR_TAG_SET_MIN_MASK 0x001F0000L +#define GDC1_A2S_MISC_CNTL__RD_TAG_SET_MIN_MASK 0x03E00000L +#define GDC1_A2S_MISC_CNTL__WRR_LRG_MODE_MASK 0x04000000L +#define GDC1_A2S_MISC_CNTL__WRR_LRG_COUNTER_MODE_MASK 0x08000000L +//GDC1_SHUB_REGS_IF_CTL +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT 0x1 +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L +#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK 0x00000002L +//GDC1_NGDC_MGCG_CTRL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT 0xe +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L +#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK 0x00004000L +//GDC1_NGDC_RESERVED_0 +#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NGDC_RESERVED_1 +#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL +//GDC1_NBIF_GFX_DOORBELL_STATUS +#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0 +#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x0000FFFFL +//GDC1_ATDMA_MISC_CNTL +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0 +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1 +#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10 +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18 +#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L +#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L +#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL +#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L +#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L +//GDC1_S2A_MISC_CNTL +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT 0x3 +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8 +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT 0xf +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10 +#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK 0x00000008L +#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L +#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L +#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L +#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK 0x00008000L +#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L +//GDC1_NGDC_EARLY_WAKEUP_CTRL +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2 +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L +#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L +//GDC1_NGDC_PG_MISC_CTRL +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10 +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18 +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L +#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L +//GDC1_NGDC_PGMST_CTRL +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8 +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L +#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L +//GDC1_NGDC_PGSLV_CTRL +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0 +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5 +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L +#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L + + +// addressBlock: aid_nbio_nbif0_gdc_sec_GDCSEC_DEC +//XCC_DOORBELL_FENCE +#define XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE__SHIFT 0x0 +#define XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE__SHIFT 0x1 +#define XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE__SHIFT 0x2 +#define XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE__SHIFT 0x3 +#define XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE__SHIFT 0x4 +#define XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE__SHIFT 0x5 +#define XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE__SHIFT 0x6 +#define XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE__SHIFT 0x7 +#define XCC_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT 0x10 +#define XCC_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT 0x11 +#define XCC_DOORBELL_FENCE__CP_0_SENT__SHIFT 0x12 +#define XCC_DOORBELL_FENCE__CP_1_SENT__SHIFT 0x13 +#define XCC_DOORBELL_FENCE__CP_2_SENT__SHIFT 0x14 +#define XCC_DOORBELL_FENCE__CP_3_SENT__SHIFT 0x15 +#define XCC_DOORBELL_FENCE__CP_4_SENT__SHIFT 0x16 +#define XCC_DOORBELL_FENCE__CP_5_SENT__SHIFT 0x17 +#define XCC_DOORBELL_FENCE__CP_6_SENT__SHIFT 0x18 +#define XCC_DOORBELL_FENCE__CP_7_SENT__SHIFT 0x19 +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT 0x1a +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT 0x1b +#define XCC_DOORBELL_FENCE__XCC_0_DOORBELL_FENCE_MASK 0x00000001L +#define XCC_DOORBELL_FENCE__XCC_1_DOORBELL_FENCE_MASK 0x00000002L +#define XCC_DOORBELL_FENCE__XCC_2_DOORBELL_FENCE_MASK 0x00000004L +#define XCC_DOORBELL_FENCE__XCC_3_DOORBELL_FENCE_MASK 0x00000008L +#define XCC_DOORBELL_FENCE__XCC_4_DOORBELL_FENCE_MASK 0x00000010L +#define XCC_DOORBELL_FENCE__XCC_5_DOORBELL_FENCE_MASK 0x00000020L +#define XCC_DOORBELL_FENCE__XCC_6_DOORBELL_FENCE_MASK 0x00000040L +#define XCC_DOORBELL_FENCE__XCC_7_DOORBELL_FENCE_MASK 0x00000080L +#define XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK 0x00010000L +#define XCC_DOORBELL_FENCE__RMOTE_CP_SENT_MASK 0x00020000L +#define XCC_DOORBELL_FENCE__CP_0_SENT_MASK 0x00040000L +#define XCC_DOORBELL_FENCE__CP_1_SENT_MASK 0x00080000L +#define XCC_DOORBELL_FENCE__CP_2_SENT_MASK 0x00100000L +#define XCC_DOORBELL_FENCE__CP_3_SENT_MASK 0x00200000L +#define XCC_DOORBELL_FENCE__CP_4_SENT_MASK 0x00400000L +#define XCC_DOORBELL_FENCE__CP_5_SENT_MASK 0x00800000L +#define XCC_DOORBELL_FENCE__CP_6_SENT_MASK 0x01000000L +#define XCC_DOORBELL_FENCE__CP_7_SENT_MASK 0x02000000L +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK 0x04000000L +#define XCC_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK 0x08000000L + + +// addressBlock: aid_nbio_nbif0_gdc_rst_GDCRST_DEC +//SHUB_PF_FLR_RST +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L +#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L +//SHUB_GFX_DRV_VPU_RST +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L +//SHUB_LINK_RESET +#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0 +#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1 +#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2 +#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3 +#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L +#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L +#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L +#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L +//SHUB_HARD_RST_CTRL +#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SOFT_RST_CTRL +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5 +#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L +#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L +#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L +#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK 0x00000008L +#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L +#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L +//SHUB_SDP_PORT_RST +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT 0x0 +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1 +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2 +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3 +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4 +#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6 +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8 +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9 +#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST__SHIFT 0xa +#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST__SHIFT 0xb +#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST__SHIFT 0xc +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT 0xd +#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18 +#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK 0x00000001L +#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L +#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L +#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L +#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L +#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L +#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L +#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L +#define SHUB_SDP_PORT_RST__MPDMATF_DMA_SDP_PORT_RST_MASK 0x00000400L +#define SHUB_SDP_PORT_RST__MPDMAPM_DMA_SDP_PORT_RST_MASK 0x00000800L +#define SHUB_SDP_PORT_RST__MPDMATF_HST_SDP_PORT_RST_MASK 0x00001000L +#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK 0x00002000L +#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L + + +// addressBlock: aid_nbio_nbif0_syshub_mmreg_syshubdirect +//HST_CLK0_SW0_CL0_CNTL +#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL0_CNTL +#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL1_CNTL +#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//HST_CLK0_SW1_CL2_CNTL +#define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +//DMA_CLK0_SW0_CL0_CNTL +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//DMA_CLK0_SW0_CL1_CNTL +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L +#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK 0x00000100L +#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK 0x00001E00L +#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK 0x00FF0000L +#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK 0xFF000000L +//NIC400_1_ASIB_0_FN_MOD +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_1_IB_0_FN_MOD +#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_2_ASIB_0_FN_MOD +#define NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_2_ASIB_0_QOS_CNTL +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_2_ASIB_0_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_2_ASIB_0_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_2_ASIB_0_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_2_ASIB_0_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_2_ASIB_0_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_2_ASIB_0_MAX_OT +#define NIC400_2_ASIB_0_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_0_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_0_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_2_ASIB_0_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_2_ASIB_0_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_0_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_2_ASIB_0_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_2_ASIB_0_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_2_ASIB_0_MAX_COMB_OT +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_2_ASIB_0_AW_P +#define NIC400_2_ASIB_0_AW_P__aw_p__SHIFT 0x18 +#define NIC400_2_ASIB_0_AW_P__aw_p_MASK 0xFF000000L +//NIC400_2_ASIB_0_AW_B +#define NIC400_2_ASIB_0_AW_B__aw_b__SHIFT 0x0 +#define NIC400_2_ASIB_0_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_0_AW_R +#define NIC400_2_ASIB_0_AW_R__aw_r__SHIFT 0x14 +#define NIC400_2_ASIB_0_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_2_ASIB_0_AR_P +#define NIC400_2_ASIB_0_AR_P__ar_p__SHIFT 0x18 +#define NIC400_2_ASIB_0_AR_P__ar_p_MASK 0xFF000000L +//NIC400_2_ASIB_0_AR_B +#define NIC400_2_ASIB_0_AR_B__ar_b__SHIFT 0x0 +#define NIC400_2_ASIB_0_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_0_AR_R +#define NIC400_2_ASIB_0_AR_R__ar_r__SHIFT 0x14 +#define NIC400_2_ASIB_0_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_2_ASIB_0_TARGET_FC +#define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_2_ASIB_0_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_2_ASIB_0_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_2_ASIB_0_KI_FC +#define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_2_ASIB_0_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_2_ASIB_0_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_2_ASIB_0_QOS_RANGE +#define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_2_ASIB_0_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_2_ASIB_0_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_2_ASIB_0_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_2_ASIB_0_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_2_ASIB_1_FN_MOD +#define NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK 0x00000002L +//NIC400_2_ASIB_1_QOS_CNTL +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT 0x0 +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT 0x1 +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT 0x2 +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT 0x3 +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT 0x4 +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT 0x5 +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT 0x6 +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT 0x7 +#define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT 0x10 +#define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT 0x14 +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_rate_MASK 0x00000001L +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_rate_MASK 0x00000002L +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_rate_MASK 0x00000004L +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_fc_MASK 0x00000008L +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_fc_MASK 0x00000010L +#define NIC400_2_ASIB_1_QOS_CNTL__en_aw_ot_MASK 0x00000020L +#define NIC400_2_ASIB_1_QOS_CNTL__en_ar_ot_MASK 0x00000040L +#define NIC400_2_ASIB_1_QOS_CNTL__en_awar_ot_MASK 0x00000080L +#define NIC400_2_ASIB_1_QOS_CNTL__mode_aw_fc_MASK 0x00010000L +#define NIC400_2_ASIB_1_QOS_CNTL__mode_ar_fc_MASK 0x00100000L +//NIC400_2_ASIB_1_MAX_OT +#define NIC400_2_ASIB_1_MAX_OT__aw_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_1_MAX_OT__aw_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_1_MAX_OT__ar_max_otf__SHIFT 0x10 +#define NIC400_2_ASIB_1_MAX_OT__ar_max_oti__SHIFT 0x18 +#define NIC400_2_ASIB_1_MAX_OT__aw_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_1_MAX_OT__aw_max_oti_MASK 0x00003F00L +#define NIC400_2_ASIB_1_MAX_OT__ar_max_otf_MASK 0x00FF0000L +#define NIC400_2_ASIB_1_MAX_OT__ar_max_oti_MASK 0x3F000000L +//NIC400_2_ASIB_1_MAX_COMB_OT +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT 0x0 +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT 0x8 +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK 0x000000FFL +#define NIC400_2_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK 0x00007F00L +//NIC400_2_ASIB_1_AW_P +#define NIC400_2_ASIB_1_AW_P__aw_p__SHIFT 0x18 +#define NIC400_2_ASIB_1_AW_P__aw_p_MASK 0xFF000000L +//NIC400_2_ASIB_1_AW_B +#define NIC400_2_ASIB_1_AW_B__aw_b__SHIFT 0x0 +#define NIC400_2_ASIB_1_AW_B__aw_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_1_AW_R +#define NIC400_2_ASIB_1_AW_R__aw_r__SHIFT 0x14 +#define NIC400_2_ASIB_1_AW_R__aw_r_MASK 0xFFF00000L +//NIC400_2_ASIB_1_AR_P +#define NIC400_2_ASIB_1_AR_P__ar_p__SHIFT 0x18 +#define NIC400_2_ASIB_1_AR_P__ar_p_MASK 0xFF000000L +//NIC400_2_ASIB_1_AR_B +#define NIC400_2_ASIB_1_AR_B__ar_b__SHIFT 0x0 +#define NIC400_2_ASIB_1_AR_B__ar_b_MASK 0x0000FFFFL +//NIC400_2_ASIB_1_AR_R +#define NIC400_2_ASIB_1_AR_R__ar_r__SHIFT 0x14 +#define NIC400_2_ASIB_1_AR_R__ar_r_MASK 0xFFF00000L +//NIC400_2_ASIB_1_TARGET_FC +#define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT 0x10 +#define NIC400_2_ASIB_1_TARGET_FC__aw_tgt_latency_MASK 0x00000FFFL +#define NIC400_2_ASIB_1_TARGET_FC__ar_tgt_latency_MASK 0x0FFF0000L +//NIC400_2_ASIB_1_KI_FC +#define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency__SHIFT 0x0 +#define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency__SHIFT 0x8 +#define NIC400_2_ASIB_1_KI_FC__aw_tgt_latency_MASK 0x00000007L +#define NIC400_2_ASIB_1_KI_FC__ar_tgt_latency_MASK 0x00000700L +//NIC400_2_ASIB_1_QOS_RANGE +#define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT 0x0 +#define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT 0x8 +#define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT 0x10 +#define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT 0x18 +#define NIC400_2_ASIB_1_QOS_RANGE__aw_min_qos_MASK 0x0000000FL +#define NIC400_2_ASIB_1_QOS_RANGE__aw_max_qos_MASK 0x00000F00L +#define NIC400_2_ASIB_1_QOS_RANGE__ar_min_qos_MASK 0x000F0000L +#define NIC400_2_ASIB_1_QOS_RANGE__ar_max_qos_MASK 0x0F000000L +//NIC400_2_IB_0_FN_MOD +#define NIC400_2_IB_0_FN_MOD__read_iss_override__SHIFT 0x0 +#define NIC400_2_IB_0_FN_MOD__write_iss_override__SHIFT 0x1 +#define NIC400_2_IB_0_FN_MOD__read_iss_override_MASK 0x00000001L +#define NIC400_2_IB_0_FN_MOD__write_iss_override_MASK 0x00000002L + + +// addressBlock: aid_nbio_iohub_nb_nbcfg_nb_cfgdec +//NB_NBCFG0_NBCFG_SCRATCH_4 +#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4__SHIFT 0x0 +#define NB_NBCFG0_NBCFG_SCRATCH_4__NBCFG_SCRATCH_4_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_misc_misc_cfgdec +//NB_CNTL +#define NB_CNTL__HWINIT_WR_LOCK__SHIFT 0x7 +#define NB_CNTL__HWINIT_WR_LOCK_MASK 0x00000080L +//NB_SPARE1 +#define NB_SPARE1__NB_SPARE1_RW__SHIFT 0x0 +#define NB_SPARE1__NB_SPARE1_RW_MASK 0xFFFFFFFFL +//NB_SPARE2 +#define NB_SPARE2__NB_SPARE2_RW1C_0__SHIFT 0x0 +#define NB_SPARE2__NB_SPARE2_RW1C_1__SHIFT 0x1 +#define NB_SPARE2__NB_SPARE2_RW1C_2__SHIFT 0x2 +#define NB_SPARE2__NB_SPARE2_RW1C_3__SHIFT 0x3 +#define NB_SPARE2__NB_SPARE2_RW1C_4__SHIFT 0x4 +#define NB_SPARE2__NB_SPARE2_RW1C_5__SHIFT 0x5 +#define NB_SPARE2__NB_SPARE2_RW1C_6__SHIFT 0x6 +#define NB_SPARE2__NB_SPARE2_RW1C_7__SHIFT 0x7 +#define NB_SPARE2__NB_SPARE2_RW1C_8__SHIFT 0x8 +#define NB_SPARE2__NB_SPARE2_RW1C_9__SHIFT 0x9 +#define NB_SPARE2__NB_SPARE2_RW1C_10__SHIFT 0xa +#define NB_SPARE2__NB_SPARE2_RW1C_11__SHIFT 0xb +#define NB_SPARE2__NB_SPARE2_RW1C_12__SHIFT 0xc +#define NB_SPARE2__NB_SPARE2_RW1C_13__SHIFT 0xd +#define NB_SPARE2__NB_SPARE2_RW1C_14__SHIFT 0xe +#define NB_SPARE2__NB_SPARE2_RW1C_15__SHIFT 0xf +#define NB_SPARE2__NB_SPARE2_RW1C_16__SHIFT 0x10 +#define NB_SPARE2__NB_SPARE2_RW1C_17__SHIFT 0x11 +#define NB_SPARE2__NB_SPARE2_RW1C_18__SHIFT 0x12 +#define NB_SPARE2__NB_SPARE2_RW1C_19__SHIFT 0x13 +#define NB_SPARE2__NB_SPARE2_RW1C_20__SHIFT 0x14 +#define NB_SPARE2__NB_SPARE2_RW1C_21__SHIFT 0x15 +#define NB_SPARE2__NB_SPARE2_RW1C_22__SHIFT 0x16 +#define NB_SPARE2__NB_SPARE2_RW1C_23__SHIFT 0x17 +#define NB_SPARE2__NB_SPARE2_RW1C_24__SHIFT 0x18 +#define NB_SPARE2__NB_SPARE2_RW1C_25__SHIFT 0x19 +#define NB_SPARE2__NB_SPARE2_RW1C_26__SHIFT 0x1a +#define NB_SPARE2__NB_SPARE2_RW1C_27__SHIFT 0x1b +#define NB_SPARE2__NB_SPARE2_RW1C_28__SHIFT 0x1c +#define NB_SPARE2__NB_SPARE2_RW1C_29__SHIFT 0x1d +#define NB_SPARE2__NB_SPARE2_RW1C_30__SHIFT 0x1e +#define NB_SPARE2__NB_SPARE2_RW1C_31__SHIFT 0x1f +#define NB_SPARE2__NB_SPARE2_RW1C_0_MASK 0x00000001L +#define NB_SPARE2__NB_SPARE2_RW1C_1_MASK 0x00000002L +#define NB_SPARE2__NB_SPARE2_RW1C_2_MASK 0x00000004L +#define NB_SPARE2__NB_SPARE2_RW1C_3_MASK 0x00000008L +#define NB_SPARE2__NB_SPARE2_RW1C_4_MASK 0x00000010L +#define NB_SPARE2__NB_SPARE2_RW1C_5_MASK 0x00000020L +#define NB_SPARE2__NB_SPARE2_RW1C_6_MASK 0x00000040L +#define NB_SPARE2__NB_SPARE2_RW1C_7_MASK 0x00000080L +#define NB_SPARE2__NB_SPARE2_RW1C_8_MASK 0x00000100L +#define NB_SPARE2__NB_SPARE2_RW1C_9_MASK 0x00000200L +#define NB_SPARE2__NB_SPARE2_RW1C_10_MASK 0x00000400L +#define NB_SPARE2__NB_SPARE2_RW1C_11_MASK 0x00000800L +#define NB_SPARE2__NB_SPARE2_RW1C_12_MASK 0x00001000L +#define NB_SPARE2__NB_SPARE2_RW1C_13_MASK 0x00002000L +#define NB_SPARE2__NB_SPARE2_RW1C_14_MASK 0x00004000L +#define NB_SPARE2__NB_SPARE2_RW1C_15_MASK 0x00008000L +#define NB_SPARE2__NB_SPARE2_RW1C_16_MASK 0x00010000L +#define NB_SPARE2__NB_SPARE2_RW1C_17_MASK 0x00020000L +#define NB_SPARE2__NB_SPARE2_RW1C_18_MASK 0x00040000L +#define NB_SPARE2__NB_SPARE2_RW1C_19_MASK 0x00080000L +#define NB_SPARE2__NB_SPARE2_RW1C_20_MASK 0x00100000L +#define NB_SPARE2__NB_SPARE2_RW1C_21_MASK 0x00200000L +#define NB_SPARE2__NB_SPARE2_RW1C_22_MASK 0x00400000L +#define NB_SPARE2__NB_SPARE2_RW1C_23_MASK 0x00800000L +#define NB_SPARE2__NB_SPARE2_RW1C_24_MASK 0x01000000L +#define NB_SPARE2__NB_SPARE2_RW1C_25_MASK 0x02000000L +#define NB_SPARE2__NB_SPARE2_RW1C_26_MASK 0x04000000L +#define NB_SPARE2__NB_SPARE2_RW1C_27_MASK 0x08000000L +#define NB_SPARE2__NB_SPARE2_RW1C_28_MASK 0x10000000L +#define NB_SPARE2__NB_SPARE2_RW1C_29_MASK 0x20000000L +#define NB_SPARE2__NB_SPARE2_RW1C_30_MASK 0x40000000L +#define NB_SPARE2__NB_SPARE2_RW1C_31_MASK 0x80000000L +//NB_REVID +#define NB_REVID__REVISION_ID__SHIFT 0x0 +#define NB_REVID__REVISION_ID_MASK 0x000003FFL +//NBIO_LCLK_DS_MASK +#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT 0x0 +#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK 0xFFFFFFFFL +//NB_BUS_NUM_CNTL +#define NB_BUS_NUM_CNTL__NB_BUS_NUM__SHIFT 0x0 +#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode__SHIFT 0x8 +#define NB_BUS_NUM_CNTL__NB_SEGMENT__SHIFT 0x10 +#define NB_BUS_NUM_CNTL__NB_BUS_NUM_MASK 0x000000FFL +#define NB_BUS_NUM_CNTL__NB_BUS_LAT_Mode_MASK 0x00000100L +#define NB_BUS_NUM_CNTL__NB_SEGMENT_MASK 0x00FF0000L +//NB_MMIOBASE +#define NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//NB_MMIOLIMIT +#define NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//NB_LOWER_TOP_OF_DRAM2 +#define NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//NB_UPPER_TOP_OF_DRAM2 +#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000001FFL +//NB_LOWER_DRAM2_BASE +#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE__SHIFT 0x17 +#define NB_LOWER_DRAM2_BASE__LOWER_DRAM2_BASE_MASK 0xFF800000L +//NB_UPPER_DRAM2_BASE +#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE__SHIFT 0x0 +#define NB_UPPER_DRAM2_BASE__UPPER_DRAM2_BASE_MASK 0x000001FFL +//SB_LOCATION +#define SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//SW_US_LOCATION +#define SW_US_LOCATION__SW_USlocated_Port__SHIFT 0x0 +#define SW_US_LOCATION__SW_USlocated_Core__SHIFT 0x10 +#define SW_US_LOCATION__SW_USlocated_Port_MASK 0x0000FFFFL +#define SW_US_LOCATION__SW_USlocated_Core_MASK 0xFFFF0000L +//NB_PROG_DEVICE_REMAP_PBr0 +#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr1 +#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr2 +#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr3 +#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr4 +#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr5 +#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr6 +#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr7 +#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr8 +#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr10 +#define NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr10__PBr10_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr11 +#define NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr11__PBr11_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr12 +#define NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr12__PBr12_DevFnMap_MASK 0x000000FFL +//NB_PROG_DEVICE_REMAP_PBr13 +#define NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap__SHIFT 0x0 +#define NB_PROG_DEVICE_REMAP_PBr13__PBr13_DevFnMap_MASK 0x000000FFL +//SW_NMI_CNTL +#define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0 +#define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL +//SW_SMI_CNTL +#define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0 +#define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL +//SW_SCI_CNTL +#define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0 +#define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL +//APML_SW_STATUS +#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0 +#define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L +//SW_GIC_SPI_CNTL +#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0 +#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8 +#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10 +#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL +#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L +#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L +//SW_SYNCFLOOD_CNTL +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0 +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1 +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L +#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L +//NB_TOP_OF_DRAM3 +#define NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0 +#define NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f +#define NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3FFFFFFFL +#define NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000L +//CAM_CONTROL +#define CAM_CONTROL__CAM_En__SHIFT 0x0 +#define CAM_CONTROL__Op__SHIFT 0x1 +#define CAM_CONTROL__AccessType__SHIFT 0x2 +#define CAM_CONTROL__DataMatchEn__SHIFT 0x3 +#define CAM_CONTROL__VC__SHIFT 0x4 +#define CAM_CONTROL__CrossTrigger__SHIFT 0x8 +#define CAM_CONTROL__CAM_En_MASK 0x00000001L +#define CAM_CONTROL__Op_MASK 0x00000002L +#define CAM_CONTROL__AccessType_MASK 0x00000004L +#define CAM_CONTROL__DataMatchEn_MASK 0x00000008L +#define CAM_CONTROL__VC_MASK 0x00000070L +#define CAM_CONTROL__CrossTrigger_MASK 0x00000F00L +//CAM_TARGET_INDEX_ADDR_BOTTOM +#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0 +#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_ADDR_TOP +#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0 +#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_DATA +#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0 +#define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL +//CAM_TARGET_INDEX_DATA_MASK +#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0 +#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_ADDR_BOTTOM +#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0 +#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_ADDR_TOP +#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0 +#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA +#define CAM_TARGET_DATA__Data__SHIFT 0x0 +#define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL +//CAM_TARGET_DATA_MASK +#define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0 +#define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL +//P_DMA_DROPPED_LOG_LOWER +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L +#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L +//P_DMA_DROPPED_LOG_UPPER +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L +#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L +//NP_DMA_DROPPED_LOG_LOWER +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19 +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L +#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L +//NP_DMA_DROPPED_LOG_UPPER +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19 +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L +#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L +//PCIE_VDM_NODE0_CTRL4 +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0 +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8 +#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL +#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L +#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L +//PCIE_VDM_CNTL2 +#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0 +#define PCIE_VDM_CNTL2__MCTPEndpointEn__SHIFT 0x2 +#define PCIE_VDM_CNTL2__MCTPMultiSegEn__SHIFT 0x3 +#define PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT 0x4 +#define PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT 0x5 +#define PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT 0x6 +#define PCIE_VDM_CNTL2__RouteAllToMCTPMaster__SHIFT 0x7 +#define PCIE_VDM_CNTL2__MCTPMasterSeg__SHIFT 0x8 +#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10 +#define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L +#define PCIE_VDM_CNTL2__MCTPEndpointEn_MASK 0x00000004L +#define PCIE_VDM_CNTL2__MCTPMultiSegEn_MASK 0x00000008L +#define PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK 0x00000010L +#define PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK 0x00000020L +#define PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK 0x00000040L +#define PCIE_VDM_CNTL2__RouteAllToMCTPMaster_MASK 0x00000080L +#define PCIE_VDM_CNTL2__MCTPMasterSeg_MASK 0x0000FF00L +#define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L +//PCIE_VDM_CNTL3 +#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf +#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10 +#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L +#define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L +//STALL_CONTROL_XBARPORT0_0 +#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT0_1 +#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT1_0 +#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT1_1 +#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT2_0 +#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT2_1 +#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT3_0 +#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT3_1 +#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT4_0 +#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT4_1 +#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT5_0 +#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK 0x30000000L +//STALL_CONTROL_XBARPORT5_1 +#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT 0x0 +#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT 0x4 +#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT 0x8 +#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT 0xc +#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT 0x10 +#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT 0x14 +#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT 0x1c +#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK 0x00000003L +#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK 0x00000030L +#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK 0x00000300L +#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK 0x00003000L +#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK 0x00030000L +#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK 0x00300000L +#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK 0x30000000L +//NB_DRAM3_BASE +#define NB_DRAM3_BASE__DRAM3_BASE__SHIFT 0x0 +#define NB_DRAM3_BASE__DRAM3_BASE_MASK 0x3FFFFFFFL +//PSP_BASE_ADDR_LO +#define PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT 0x0 +#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT 0x8 +#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT 0x14 +#define PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK 0x00000001L +#define PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK 0x00000100L +#define PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK 0xFFF00000L +//PSP_BASE_ADDR_HI +#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT 0x0 +#define PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK 0x0000FFFFL +//SMU_BASE_ADDR_LO +#define SMU_BASE_ADDR_LO__SMU_MMIO_EN__SHIFT 0x0 +#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK__SHIFT 0x1 +#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO__SHIFT 0x14 +#define SMU_BASE_ADDR_LO__SMU_MMIO_EN_MASK 0x00000001L +#define SMU_BASE_ADDR_LO__SMU_MMIO_LOCK_MASK 0x00000002L +#define SMU_BASE_ADDR_LO__SMU_BASE_ADDR_LO_MASK 0xFFF00000L +//SMU_BASE_ADDR_HI +#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI__SHIFT 0x0 +#define SMU_BASE_ADDR_HI__SMU_BASE_ADDR_HI_MASK 0x0000FFFFL +//SCRATCH_4 +#define SCRATCH_4__SCRATCH_4__SHIFT 0x0 +#define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL +//SCRATCH_5 +#define SCRATCH_5__SCRATCH_5__SHIFT 0x0 +#define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL +//SMU_BLOCK_CPU +#define SMU_BLOCK_CPU__SMUBlockCPU_Valid__SHIFT 0x0 +#define SMU_BLOCK_CPU__SMUBlockCPU_Valid_MASK 0x00000001L +//SMU_BLOCK_CPU_STATUS +#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status__SHIFT 0x0 +#define SMU_BLOCK_CPU_STATUS__SMUBlockCPU_Status_MASK 0x00000001L +//TRAP_STATUS +#define TRAP_STATUS__TrapReqValid__SHIFT 0x0 +#define TRAP_STATUS__TrapNumber__SHIFT 0x8 +#define TRAP_STATUS__TrapS2Vld__SHIFT 0xc +#define TRAP_STATUS__TrapS2Number__SHIFT 0x10 +#define TRAP_STATUS__TrapReqValid_MASK 0x00000001L +#define TRAP_STATUS__TrapNumber_MASK 0x00000F00L +#define TRAP_STATUS__TrapS2Vld_MASK 0x00001000L +#define TRAP_STATUS__TrapS2Number_MASK 0x03FF0000L +//TRAP_REQUEST0 +#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2 +#define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL +//TRAP_REQUEST1 +#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0 +#define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL +//TRAP_REQUEST2 +#define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0 +#define TRAP_REQUEST2__TrapAttr__SHIFT 0x8 +#define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10 +#define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL +#define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L +#define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L +//TRAP_REQUEST3 +#define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0 +#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4 +#define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6 +#define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7 +#define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8 +#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9 +#define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10 +#define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L +#define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L +#define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L +#define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L +#define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L +#define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L +#define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L +//TRAP_REQUEST4 +#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0 +#define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x0000000FL +//TRAP_REQUEST5 +#define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0 +#define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4 +#define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8 +#define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L +#define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L +#define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L +//TRAP_REQUEST_DATASTRB0 +#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0 +#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATASTRB1 +#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0 +#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA0 +#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0 +#define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA1 +#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0 +#define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA2 +#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0 +#define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA3 +#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0 +#define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA4 +#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0 +#define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA5 +#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0 +#define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA6 +#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0 +#define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA7 +#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0 +#define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA8 +#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0 +#define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA9 +#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0 +#define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA10 +#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0 +#define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA11 +#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0 +#define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA12 +#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0 +#define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA13 +#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0 +#define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA14 +#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0 +#define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL +//TRAP_REQUEST_DATA15 +#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0 +#define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_CONTROL +#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0 +#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT 0x1 +#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L +#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK 0x00000002L +//TRAP_RESPONSE0 +#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0 +#define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4 +#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10 +#define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L +#define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L +#define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x00FF0000L +//TRAP_RESPONSE_DATA0 +#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0 +#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA1 +#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0 +#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA2 +#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0 +#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA3 +#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0 +#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA4 +#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0 +#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA5 +#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0 +#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA6 +#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0 +#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA7 +#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0 +#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA8 +#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0 +#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA9 +#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0 +#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA10 +#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0 +#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA11 +#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0 +#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA12 +#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0 +#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA13 +#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0 +#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA14 +#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0 +#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL +//TRAP_RESPONSE_DATA15 +#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0 +#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL +//TRAP0_CONTROL0 +#define TRAP0_CONTROL0__Trap0En__SHIFT 0x0 +#define TRAP0_CONTROL0__Trap0SMUIntr__SHIFT 0x3 +#define TRAP0_CONTROL0__Trap0Stage2Ptr__SHIFT 0xe +#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18 +#define TRAP0_CONTROL0__Trap0Stage2En__SHIFT 0x1f +#define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L +#define TRAP0_CONTROL0__Trap0SMUIntr_MASK 0x00000008L +#define TRAP0_CONTROL0__Trap0Stage2Ptr_MASK 0x00FFC000L +#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0x0F000000L +#define TRAP0_CONTROL0__Trap0Stage2En_MASK 0x80000000L +//TRAP0_ADDRESS_LO +#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2 +#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL +//TRAP0_ADDRESS_HI +#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0 +#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0xFFFFFFFFL +//TRAP0_COMMAND +#define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0 +#define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8 +#define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL +#define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L +//TRAP0_ADDRESS_LO_MASK +#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2 +#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL +//TRAP0_ADDRESS_HI_MASK +#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0 +#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0xFFFFFFFFL +//TRAP0_COMMAND_MASK +#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0 +#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8 +#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL +#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L +//TRAP1_CONTROL0 +#define TRAP1_CONTROL0__Trap1En__SHIFT 0x0 +#define TRAP1_CONTROL0__Trap1SMUIntr__SHIFT 0x3 +#define TRAP1_CONTROL0__Trap1Stage2Ptr__SHIFT 0xe +#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18 +#define TRAP1_CONTROL0__Trap1Stage2En__SHIFT 0x1f +#define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L +#define TRAP1_CONTROL0__Trap1SMUIntr_MASK 0x00000008L +#define TRAP1_CONTROL0__Trap1Stage2Ptr_MASK 0x00FFC000L +#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0x0F000000L +#define TRAP1_CONTROL0__Trap1Stage2En_MASK 0x80000000L +//TRAP1_ADDRESS_LO +#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2 +#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL +//TRAP1_ADDRESS_HI +#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0 +#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0xFFFFFFFFL +//TRAP1_COMMAND +#define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0 +#define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8 +#define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL +#define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L +//TRAP1_ADDRESS_LO_MASK +#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2 +#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL +//TRAP1_ADDRESS_HI_MASK +#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0 +#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0xFFFFFFFFL +//TRAP1_COMMAND_MASK +#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0 +#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8 +#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL +#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L +//TRAP2_CONTROL0 +#define TRAP2_CONTROL0__Trap2En__SHIFT 0x0 +#define TRAP2_CONTROL0__Trap2SMUIntr__SHIFT 0x3 +#define TRAP2_CONTROL0__Trap2Stage2Ptr__SHIFT 0xe +#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18 +#define TRAP2_CONTROL0__Trap2Stage2En__SHIFT 0x1f +#define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L +#define TRAP2_CONTROL0__Trap2SMUIntr_MASK 0x00000008L +#define TRAP2_CONTROL0__Trap2Stage2Ptr_MASK 0x00FFC000L +#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0x0F000000L +#define TRAP2_CONTROL0__Trap2Stage2En_MASK 0x80000000L +//TRAP2_ADDRESS_LO +#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2 +#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL +//TRAP2_ADDRESS_HI +#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0 +#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0xFFFFFFFFL +//TRAP2_COMMAND +#define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0 +#define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8 +#define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL +#define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L +//TRAP2_ADDRESS_LO_MASK +#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2 +#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL +//TRAP2_ADDRESS_HI_MASK +#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0 +#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0xFFFFFFFFL +//TRAP2_COMMAND_MASK +#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0 +#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8 +#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL +#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L +//TRAP3_CONTROL0 +#define TRAP3_CONTROL0__Trap3En__SHIFT 0x0 +#define TRAP3_CONTROL0__Trap3SMUIntr__SHIFT 0x3 +#define TRAP3_CONTROL0__Trap3Stage2Ptr__SHIFT 0xe +#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18 +#define TRAP3_CONTROL0__Trap3Stage2En__SHIFT 0x1f +#define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L +#define TRAP3_CONTROL0__Trap3SMUIntr_MASK 0x00000008L +#define TRAP3_CONTROL0__Trap3Stage2Ptr_MASK 0x00FFC000L +#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0x0F000000L +#define TRAP3_CONTROL0__Trap3Stage2En_MASK 0x80000000L +//TRAP3_ADDRESS_LO +#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2 +#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL +//TRAP3_ADDRESS_HI +#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0 +#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0xFFFFFFFFL +//TRAP3_COMMAND +#define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0 +#define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8 +#define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL +#define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L +//TRAP3_ADDRESS_LO_MASK +#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2 +#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL +//TRAP3_ADDRESS_HI_MASK +#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0 +#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0xFFFFFFFFL +//TRAP3_COMMAND_MASK +#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0 +#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8 +#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL +#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L +//TRAP4_CONTROL0 +#define TRAP4_CONTROL0__Trap4En__SHIFT 0x0 +#define TRAP4_CONTROL0__Trap4SMUIntr__SHIFT 0x3 +#define TRAP4_CONTROL0__Trap4Stage2Ptr__SHIFT 0xe +#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18 +#define TRAP4_CONTROL0__Trap4Stage2En__SHIFT 0x1f +#define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L +#define TRAP4_CONTROL0__Trap4SMUIntr_MASK 0x00000008L +#define TRAP4_CONTROL0__Trap4Stage2Ptr_MASK 0x00FFC000L +#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0x0F000000L +#define TRAP4_CONTROL0__Trap4Stage2En_MASK 0x80000000L +//TRAP4_ADDRESS_LO +#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2 +#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL +//TRAP4_ADDRESS_HI +#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0 +#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0xFFFFFFFFL +//TRAP4_COMMAND +#define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0 +#define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8 +#define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL +#define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L +//TRAP4_ADDRESS_LO_MASK +#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2 +#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL +//TRAP4_ADDRESS_HI_MASK +#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0 +#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0xFFFFFFFFL +//TRAP4_COMMAND_MASK +#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0 +#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8 +#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL +#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L +//TRAP5_CONTROL0 +#define TRAP5_CONTROL0__Trap5En__SHIFT 0x0 +#define TRAP5_CONTROL0__Trap5SMUIntr__SHIFT 0x3 +#define TRAP5_CONTROL0__Trap5Stage2Ptr__SHIFT 0xe +#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18 +#define TRAP5_CONTROL0__Trap5Stage2En__SHIFT 0x1f +#define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L +#define TRAP5_CONTROL0__Trap5SMUIntr_MASK 0x00000008L +#define TRAP5_CONTROL0__Trap5Stage2Ptr_MASK 0x00FFC000L +#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0x0F000000L +#define TRAP5_CONTROL0__Trap5Stage2En_MASK 0x80000000L +//TRAP5_ADDRESS_LO +#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2 +#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL +//TRAP5_ADDRESS_HI +#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0 +#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0xFFFFFFFFL +//TRAP5_COMMAND +#define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0 +#define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8 +#define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL +#define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L +//TRAP5_ADDRESS_LO_MASK +#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2 +#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL +//TRAP5_ADDRESS_HI_MASK +#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0 +#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0xFFFFFFFFL +//TRAP5_COMMAND_MASK +#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0 +#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8 +#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL +#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L +//TRAP6_CONTROL0 +#define TRAP6_CONTROL0__Trap6En__SHIFT 0x0 +#define TRAP6_CONTROL0__Trap6SMUIntr__SHIFT 0x3 +#define TRAP6_CONTROL0__Trap6Stage2Ptr__SHIFT 0xe +#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18 +#define TRAP6_CONTROL0__Trap6Stage2En__SHIFT 0x1f +#define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L +#define TRAP6_CONTROL0__Trap6SMUIntr_MASK 0x00000008L +#define TRAP6_CONTROL0__Trap6Stage2Ptr_MASK 0x00FFC000L +#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0x0F000000L +#define TRAP6_CONTROL0__Trap6Stage2En_MASK 0x80000000L +//TRAP6_ADDRESS_LO +#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2 +#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL +//TRAP6_ADDRESS_HI +#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0 +#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0xFFFFFFFFL +//TRAP6_COMMAND +#define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0 +#define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8 +#define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL +#define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L +//TRAP6_ADDRESS_LO_MASK +#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2 +#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL +//TRAP6_ADDRESS_HI_MASK +#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0 +#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0xFFFFFFFFL +//TRAP6_COMMAND_MASK +#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0 +#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8 +#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL +#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L +//TRAP7_CONTROL0 +#define TRAP7_CONTROL0__Trap7En__SHIFT 0x0 +#define TRAP7_CONTROL0__Trap7SMUIntr__SHIFT 0x3 +#define TRAP7_CONTROL0__Trap7Stage2Ptr__SHIFT 0xe +#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18 +#define TRAP7_CONTROL0__Trap7Stage2En__SHIFT 0x1f +#define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L +#define TRAP7_CONTROL0__Trap7SMUIntr_MASK 0x00000008L +#define TRAP7_CONTROL0__Trap7Stage2Ptr_MASK 0x00FFC000L +#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0x0F000000L +#define TRAP7_CONTROL0__Trap7Stage2En_MASK 0x80000000L +//TRAP7_ADDRESS_LO +#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2 +#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL +//TRAP7_ADDRESS_HI +#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0 +#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0xFFFFFFFFL +//TRAP7_COMMAND +#define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0 +#define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8 +#define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL +#define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L +//TRAP7_ADDRESS_LO_MASK +#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2 +#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL +//TRAP7_ADDRESS_HI_MASK +#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0 +#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0xFFFFFFFFL +//TRAP7_COMMAND_MASK +#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0 +#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8 +#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL +#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L +//TRAP8_CONTROL0 +#define TRAP8_CONTROL0__Trap8En__SHIFT 0x0 +#define TRAP8_CONTROL0__Trap8SMUIntr__SHIFT 0x3 +#define TRAP8_CONTROL0__Trap8Stage2Ptr__SHIFT 0xe +#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18 +#define TRAP8_CONTROL0__Trap8Stage2En__SHIFT 0x1f +#define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L +#define TRAP8_CONTROL0__Trap8SMUIntr_MASK 0x00000008L +#define TRAP8_CONTROL0__Trap8Stage2Ptr_MASK 0x00FFC000L +#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0x0F000000L +#define TRAP8_CONTROL0__Trap8Stage2En_MASK 0x80000000L +//TRAP8_ADDRESS_LO +#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2 +#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL +//TRAP8_ADDRESS_HI +#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0 +#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0xFFFFFFFFL +//TRAP8_COMMAND +#define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0 +#define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8 +#define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL +#define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L +//TRAP8_ADDRESS_LO_MASK +#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2 +#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL +//TRAP8_ADDRESS_HI_MASK +#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0 +#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0xFFFFFFFFL +//TRAP8_COMMAND_MASK +#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0 +#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8 +#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL +#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L +//TRAP9_CONTROL0 +#define TRAP9_CONTROL0__Trap9En__SHIFT 0x0 +#define TRAP9_CONTROL0__Trap9SMUIntr__SHIFT 0x3 +#define TRAP9_CONTROL0__Trap9Stage2Ptr__SHIFT 0xe +#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18 +#define TRAP9_CONTROL0__Trap9Stage2En__SHIFT 0x1f +#define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L +#define TRAP9_CONTROL0__Trap9SMUIntr_MASK 0x00000008L +#define TRAP9_CONTROL0__Trap9Stage2Ptr_MASK 0x00FFC000L +#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0x0F000000L +#define TRAP9_CONTROL0__Trap9Stage2En_MASK 0x80000000L +//TRAP9_ADDRESS_LO +#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2 +#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL +//TRAP9_ADDRESS_HI +#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0 +#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0xFFFFFFFFL +//TRAP9_COMMAND +#define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0 +#define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8 +#define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL +#define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L +//TRAP9_ADDRESS_LO_MASK +#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2 +#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL +//TRAP9_ADDRESS_HI_MASK +#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0 +#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0xFFFFFFFFL +//TRAP9_COMMAND_MASK +#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0 +#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8 +#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL +#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L +//TRAP10_CONTROL0 +#define TRAP10_CONTROL0__Trap10En__SHIFT 0x0 +#define TRAP10_CONTROL0__Trap10SMUIntr__SHIFT 0x3 +#define TRAP10_CONTROL0__Trap10Stage2Ptr__SHIFT 0xe +#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18 +#define TRAP10_CONTROL0__Trap10Stage2En__SHIFT 0x1f +#define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L +#define TRAP10_CONTROL0__Trap10SMUIntr_MASK 0x00000008L +#define TRAP10_CONTROL0__Trap10Stage2Ptr_MASK 0x00FFC000L +#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0x0F000000L +#define TRAP10_CONTROL0__Trap10Stage2En_MASK 0x80000000L +//TRAP10_ADDRESS_LO +#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2 +#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL +//TRAP10_ADDRESS_HI +#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0 +#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0xFFFFFFFFL +//TRAP10_COMMAND +#define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0 +#define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8 +#define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL +#define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L +//TRAP10_ADDRESS_LO_MASK +#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2 +#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL +//TRAP10_ADDRESS_HI_MASK +#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0 +#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0xFFFFFFFFL +//TRAP10_COMMAND_MASK +#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0 +#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8 +#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL +#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L +//TRAP11_CONTROL0 +#define TRAP11_CONTROL0__Trap11En__SHIFT 0x0 +#define TRAP11_CONTROL0__Trap11SMUIntr__SHIFT 0x3 +#define TRAP11_CONTROL0__Trap11Stage2Ptr__SHIFT 0xe +#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18 +#define TRAP11_CONTROL0__Trap11Stage2En__SHIFT 0x1f +#define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L +#define TRAP11_CONTROL0__Trap11SMUIntr_MASK 0x00000008L +#define TRAP11_CONTROL0__Trap11Stage2Ptr_MASK 0x00FFC000L +#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0x0F000000L +#define TRAP11_CONTROL0__Trap11Stage2En_MASK 0x80000000L +//TRAP11_ADDRESS_LO +#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2 +#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL +//TRAP11_ADDRESS_HI +#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0 +#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0xFFFFFFFFL +//TRAP11_COMMAND +#define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0 +#define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8 +#define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL +#define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L +//TRAP11_ADDRESS_LO_MASK +#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2 +#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL +//TRAP11_ADDRESS_HI_MASK +#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0 +#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0xFFFFFFFFL +//TRAP11_COMMAND_MASK +#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0 +#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8 +#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL +#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L +//TRAP12_CONTROL0 +#define TRAP12_CONTROL0__Trap12En__SHIFT 0x0 +#define TRAP12_CONTROL0__Trap12SMUIntr__SHIFT 0x3 +#define TRAP12_CONTROL0__Trap12Stage2Ptr__SHIFT 0xe +#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18 +#define TRAP12_CONTROL0__Trap12Stage2En__SHIFT 0x1f +#define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L +#define TRAP12_CONTROL0__Trap12SMUIntr_MASK 0x00000008L +#define TRAP12_CONTROL0__Trap12Stage2Ptr_MASK 0x00FFC000L +#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0x0F000000L +#define TRAP12_CONTROL0__Trap12Stage2En_MASK 0x80000000L +//TRAP12_ADDRESS_LO +#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2 +#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL +//TRAP12_ADDRESS_HI +#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0 +#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0xFFFFFFFFL +//TRAP12_COMMAND +#define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0 +#define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8 +#define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL +#define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L +//TRAP12_ADDRESS_LO_MASK +#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2 +#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL +//TRAP12_ADDRESS_HI_MASK +#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0 +#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0xFFFFFFFFL +//TRAP12_COMMAND_MASK +#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0 +#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8 +#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL +#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L +//TRAP13_CONTROL0 +#define TRAP13_CONTROL0__Trap13En__SHIFT 0x0 +#define TRAP13_CONTROL0__Trap13SMUIntr__SHIFT 0x3 +#define TRAP13_CONTROL0__Trap13Stage2Ptr__SHIFT 0xe +#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18 +#define TRAP13_CONTROL0__Trap13Stage2En__SHIFT 0x1f +#define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L +#define TRAP13_CONTROL0__Trap13SMUIntr_MASK 0x00000008L +#define TRAP13_CONTROL0__Trap13Stage2Ptr_MASK 0x00FFC000L +#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0x0F000000L +#define TRAP13_CONTROL0__Trap13Stage2En_MASK 0x80000000L +//TRAP13_ADDRESS_LO +#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2 +#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL +//TRAP13_ADDRESS_HI +#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0 +#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0xFFFFFFFFL +//TRAP13_COMMAND +#define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0 +#define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8 +#define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL +#define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L +//TRAP13_ADDRESS_LO_MASK +#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2 +#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL +//TRAP13_ADDRESS_HI_MASK +#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0 +#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0xFFFFFFFFL +//TRAP13_COMMAND_MASK +#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0 +#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8 +#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL +#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L +//TRAP14_CONTROL0 +#define TRAP14_CONTROL0__Trap14En__SHIFT 0x0 +#define TRAP14_CONTROL0__Trap14SMUIntr__SHIFT 0x3 +#define TRAP14_CONTROL0__Trap14Stage2Ptr__SHIFT 0xe +#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18 +#define TRAP14_CONTROL0__Trap14Stage2En__SHIFT 0x1f +#define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L +#define TRAP14_CONTROL0__Trap14SMUIntr_MASK 0x00000008L +#define TRAP14_CONTROL0__Trap14Stage2Ptr_MASK 0x00FFC000L +#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0x0F000000L +#define TRAP14_CONTROL0__Trap14Stage2En_MASK 0x80000000L +//TRAP14_ADDRESS_LO +#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2 +#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL +//TRAP14_ADDRESS_HI +#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0 +#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0xFFFFFFFFL +//TRAP14_COMMAND +#define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0 +#define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8 +#define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL +#define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L +//TRAP14_ADDRESS_LO_MASK +#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2 +#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL +//TRAP14_ADDRESS_HI_MASK +#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0 +#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0xFFFFFFFFL +//TRAP14_COMMAND_MASK +#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0 +#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8 +#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL +#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L +//TRAP15_CONTROL0 +#define TRAP15_CONTROL0__Trap15En__SHIFT 0x0 +#define TRAP15_CONTROL0__Trap15SMUIntr__SHIFT 0x3 +#define TRAP15_CONTROL0__Trap15Stage2Ptr__SHIFT 0xe +#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18 +#define TRAP15_CONTROL0__Trap15Stage2En__SHIFT 0x1f +#define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L +#define TRAP15_CONTROL0__Trap15SMUIntr_MASK 0x00000008L +#define TRAP15_CONTROL0__Trap15Stage2Ptr_MASK 0x00FFC000L +#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0x0F000000L +#define TRAP15_CONTROL0__Trap15Stage2En_MASK 0x80000000L +//TRAP15_ADDRESS_LO +#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2 +#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL +//TRAP15_ADDRESS_HI +#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0 +#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0xFFFFFFFFL +//TRAP15_COMMAND +#define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0 +#define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8 +#define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL +#define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L +//TRAP15_ADDRESS_LO_MASK +#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2 +#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL +//TRAP15_ADDRESS_HI_MASK +#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0 +#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0xFFFFFFFFL +//TRAP15_COMMAND_MASK +#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0 +#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8 +#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL +#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L +//SB_COMMAND +#define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L +//SB_SUB_BUS_NUMBER_LATENCY +#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +//SB_IO_BASE_LIMIT +#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//SB_MEM_BASE_LIMIT +#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//SB_PREF_BASE_LIMIT +#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//SB_PREF_BASE_UPPER +#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//SB_PREF_LIMIT_UPPER +#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//SB_IO_BASE_LIMIT_HI +#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//SB_IRQ_BRIDGE_CNTL +#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +//SB_EXT_BRIDGE_CNTL +#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//SB_PMI_STATUS_CNTL +#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L +//SB_SLOT_CAP +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +//SB_ROOT_CNTL +#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//SB_DEVICE_CNTL2 +#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +//MCA_SMN_INT_REQ_ADDR +#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT 0x0 +#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK 0x000FFFFFL +//MCA_SMN_INT_MCM_ADDR +#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT 0x0 +#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK 0x000000FFL +//MCA_SMN_INT_APERTUREID +#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT 0x0 +#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK 0x00000FFFL +//MCA_SMN_INT_CONTROL +#define MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT 0x0 +#define MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK 0x0000000FL + + +// addressBlock: aid_nbio_iohub_nb_rascfg_ras_cfgdec +//PARITY_CONTROL_0 +#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0 +#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10 +#define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL +#define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L +//PARITY_CONTROL_1 +#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0 +#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8 +#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb +#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10 +#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e +#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f +#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL +#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L +#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L +#define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L +#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L +#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L +//PARITY_SEVERITY_CONTROL_UNCORR_0 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT 0xa +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT 0xc +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT 0xe +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8__SHIFT 0x10 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9__SHIFT 0x12 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10__SHIFT 0x14 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11__SHIFT 0x16 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12__SHIFT 0x18 +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13__SHIFT 0x1a +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14__SHIFT 0x1c +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15__SHIFT 0x1e +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK 0x00000C00L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK 0x00003000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK 0x0000C000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp8_MASK 0x00030000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp9_MASK 0x000C0000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp10_MASK 0x00300000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp11_MASK 0x00C00000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp12_MASK 0x03000000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp13_MASK 0x0C000000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp14_MASK 0x30000000L +#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp15_MASK 0xC0000000L +//PARITY_SEVERITY_CONTROL_CORR_0 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT 0xa +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT 0xc +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT 0xe +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8__SHIFT 0x10 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9__SHIFT 0x12 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10__SHIFT 0x14 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11__SHIFT 0x16 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12__SHIFT 0x18 +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13__SHIFT 0x1a +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14__SHIFT 0x1c +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15__SHIFT 0x1e +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK 0x00000C00L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK 0x00003000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK 0x0000C000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp8_MASK 0x00030000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp9_MASK 0x000C0000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp10_MASK 0x00300000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp11_MASK 0x00C00000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp12_MASK 0x03000000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp13_MASK 0x0C000000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp14_MASK 0x30000000L +#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp15_MASK 0xC0000000L +//PARITY_SEVERITY_CONTROL_UCP_0 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT 0xa +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT 0xc +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT 0xe +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8__SHIFT 0x10 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9__SHIFT 0x12 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10__SHIFT 0x14 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11__SHIFT 0x16 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12__SHIFT 0x18 +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK 0x00000C00L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK 0x00003000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK 0x0000C000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp8_MASK 0x00030000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp9_MASK 0x000C0000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp10_MASK 0x00300000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp11_MASK 0x00C00000L +#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp12_MASK 0x03000000L +//RAS_GLOBAL_STATUS_LO +#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0 +#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1 +#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2 +#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7 +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8 +#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9 +#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa +#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb +#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd +#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf +#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L +#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L +#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L +#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L +#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L +#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L +#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L +#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L +#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L +#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L +#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L +//RAS_GLOBAL_STATUS_HI +#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT 0x1 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT 0x2 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT 0x3 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT 0x4 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT 0x5 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT 0x6 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortHErr__SHIFT 0x7 +#define RAS_GLOBAL_STATUS_HI__PCIE0PortIErr__SHIFT 0x8 +#define RAS_GLOBAL_STATUS_HI__PCIE1PortAErr__SHIFT 0x9 +#define RAS_GLOBAL_STATUS_HI__PCIE1PortBErr__SHIFT 0xa +#define RAS_GLOBAL_STATUS_HI__PCIE1PortCErr__SHIFT 0xb +#define RAS_GLOBAL_STATUS_HI__PCIE1PortDErr__SHIFT 0xc +#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT 0xd +#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK 0x00000002L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK 0x00000004L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK 0x00000008L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK 0x00000010L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK 0x00000020L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK 0x00000040L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortHErr_MASK 0x00000080L +#define RAS_GLOBAL_STATUS_HI__PCIE0PortIErr_MASK 0x00000100L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortAErr_MASK 0x00000200L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortBErr_MASK 0x00000400L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortCErr_MASK 0x00000800L +#define RAS_GLOBAL_STATUS_HI__PCIE1PortDErr_MASK 0x00001000L +#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK 0x00002000L +//PARITY_ERROR_STATUS_UNCORR_GRP0 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP1 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP2 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP3 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP4 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP5 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP6 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP7 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP10 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP10__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP11 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP11__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP12 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP12__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP13 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP13__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP14 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP14__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP15 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP15__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UNCORR_GRP16 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UNCORR_GRP16__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP0 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP1 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP2 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP3 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP4 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP5 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP6 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP7 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP10 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP10__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP11 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP11__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP12 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP12__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP13 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP13__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP14 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP14__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP15 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP15__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP16 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP16__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_CORR_GRP17 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_CORR_GRP17__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP0 +#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP1 +#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP2 +#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP3 +#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP4 +#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP5 +#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP5__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP5__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP6 +#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP6__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP6__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP7 +#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP7__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP7__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP10 +#define PARITY_COUNTER_CORR_GRP10__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP10__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP10__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP10__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP11 +#define PARITY_COUNTER_CORR_GRP11__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP11__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP11__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP11__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP12 +#define PARITY_COUNTER_CORR_GRP12__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP12__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP12__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP12__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP13 +#define PARITY_COUNTER_CORR_GRP13__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP13__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP13__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP13__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP14 +#define PARITY_COUNTER_CORR_GRP14__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP14__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP14__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP14__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP15 +#define PARITY_COUNTER_CORR_GRP15__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP15__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP15__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP15__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP16 +#define PARITY_COUNTER_CORR_GRP16__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP16__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP16__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP16__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_CORR_GRP17 +#define PARITY_COUNTER_CORR_GRP17__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_CORR_GRP17__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_CORR_GRP17__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_CORR_GRP17__ResetEn_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP0 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP1 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP2 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP3 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP4 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP5 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP6 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP7 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP10 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP10__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP11 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP11__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_ERROR_STATUS_UCP_GRP12 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0__SHIFT 0x0 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1__SHIFT 0x1 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2__SHIFT 0x2 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3__SHIFT 0x3 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4__SHIFT 0x4 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5__SHIFT 0x5 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6__SHIFT 0x6 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7__SHIFT 0x7 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8__SHIFT 0x8 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9__SHIFT 0x9 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10__SHIFT 0xa +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11__SHIFT 0xb +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12__SHIFT 0xc +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13__SHIFT 0xd +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14__SHIFT 0xe +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15__SHIFT 0xf +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16__SHIFT 0x10 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17__SHIFT 0x11 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18__SHIFT 0x12 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19__SHIFT 0x13 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20__SHIFT 0x14 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21__SHIFT 0x15 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22__SHIFT 0x16 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23__SHIFT 0x17 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24__SHIFT 0x18 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25__SHIFT 0x19 +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26__SHIFT 0x1a +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27__SHIFT 0x1b +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28__SHIFT 0x1c +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29__SHIFT 0x1d +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30__SHIFT 0x1e +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31__SHIFT 0x1f +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id0_MASK 0x00000001L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id1_MASK 0x00000002L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id2_MASK 0x00000004L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id3_MASK 0x00000008L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id4_MASK 0x00000010L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id5_MASK 0x00000020L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id6_MASK 0x00000040L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id7_MASK 0x00000080L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id8_MASK 0x00000100L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id9_MASK 0x00000200L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id10_MASK 0x00000400L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id11_MASK 0x00000800L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id12_MASK 0x00001000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id13_MASK 0x00002000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id14_MASK 0x00004000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id15_MASK 0x00008000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id16_MASK 0x00010000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id17_MASK 0x00020000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id18_MASK 0x00040000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id19_MASK 0x00080000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id20_MASK 0x00100000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id21_MASK 0x00200000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id22_MASK 0x00400000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id23_MASK 0x00800000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id24_MASK 0x01000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id25_MASK 0x02000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id26_MASK 0x04000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id27_MASK 0x08000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id28_MASK 0x10000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id29_MASK 0x20000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id30_MASK 0x40000000L +#define PARITY_ERROR_STATUS_UCP_GRP12__ParityErrDetected_Id31_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP0 +#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP1 +#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP2 +#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP3 +#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP4 +#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP5 +#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP5__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP5__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP6 +#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP6__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP6__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP7 +#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP7__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP7__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP10 +#define PARITY_COUNTER_UCP_GRP10__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP10__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP10__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP10__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP11 +#define PARITY_COUNTER_UCP_GRP11__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP11__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP11__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP11__ResetEn_MASK 0x80000000L +//PARITY_COUNTER_UCP_GRP12 +#define PARITY_COUNTER_UCP_GRP12__ThresholdCounter__SHIFT 0x0 +#define PARITY_COUNTER_UCP_GRP12__ResetEn__SHIFT 0x1f +#define PARITY_COUNTER_UCP_GRP12__ThresholdCounter_MASK 0x0000FFFFL +#define PARITY_COUNTER_UCP_GRP12__ResetEn_MASK 0x80000000L +//MISC_SEVERITY_CONTROL +#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4 +#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6 +#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L +#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L +//MISC_RAS_CONTROL +#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2 +#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis__SHIFT 0x3 +#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9 +#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa +#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb +#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc +#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd +#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe +#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf +#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10 +#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11 +#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L +#define MISC_RAS_CONTROL__GNB_SB_LinkNeverDis_MASK 0x00000008L +#define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L +#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L +#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L +#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L +#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L +#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L +#define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L +#define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L +#define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L +//RAS_SCRATCH_0 +#define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//RAS_SCRATCH_1 +#define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL +//ErrEvent_ACTION_CONTROL +#define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParitySerr_ACTION_CONTROL +#define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityFatal_ACTION_CONTROL +#define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityNonFatal_ACTION_CONTROL +#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//ParityCorr_ACTION_CONTROL +#define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortASerr_ACTION_CONTROL +#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntFatal_ACTION_CONTROL +#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntNonFatal_ACTION_CONTROL +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAIntCorr_ACTION_CONTROL +#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtFatal_ACTION_CONTROL +#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtNonFatal_ACTION_CONTROL +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAExtCorr_ACTION_CONTROL +#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortAParityErr_ACTION_CONTROL +#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBSerr_ACTION_CONTROL +#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntFatal_ACTION_CONTROL +#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntNonFatal_ACTION_CONTROL +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBIntCorr_ACTION_CONTROL +#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtFatal_ACTION_CONTROL +#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtNonFatal_ACTION_CONTROL +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBExtCorr_ACTION_CONTROL +#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortBParityErr_ACTION_CONTROL +#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCSerr_ACTION_CONTROL +#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntFatal_ACTION_CONTROL +#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntNonFatal_ACTION_CONTROL +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCIntCorr_ACTION_CONTROL +#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtFatal_ACTION_CONTROL +#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtNonFatal_ACTION_CONTROL +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCExtCorr_ACTION_CONTROL +#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortCParityErr_ACTION_CONTROL +#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDSerr_ACTION_CONTROL +#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntFatal_ACTION_CONTROL +#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntNonFatal_ACTION_CONTROL +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDIntCorr_ACTION_CONTROL +#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtFatal_ACTION_CONTROL +#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtNonFatal_ACTION_CONTROL +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDExtCorr_ACTION_CONTROL +#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortDParityErr_ACTION_CONTROL +#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortESerr_ACTION_CONTROL +#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntFatal_ACTION_CONTROL +#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntNonFatal_ACTION_CONTROL +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEIntCorr_ACTION_CONTROL +#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtFatal_ACTION_CONTROL +#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtNonFatal_ACTION_CONTROL +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEExtCorr_ACTION_CONTROL +#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortEParityErr_ACTION_CONTROL +#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFSerr_ACTION_CONTROL +#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntFatal_ACTION_CONTROL +#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntNonFatal_ACTION_CONTROL +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFIntCorr_ACTION_CONTROL +#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtFatal_ACTION_CONTROL +#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtNonFatal_ACTION_CONTROL +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFExtCorr_ACTION_CONTROL +#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortFParityErr_ACTION_CONTROL +#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGSerr_ACTION_CONTROL +#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntFatal_ACTION_CONTROL +#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntNonFatal_ACTION_CONTROL +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGIntCorr_ACTION_CONTROL +#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtFatal_ACTION_CONTROL +#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtNonFatal_ACTION_CONTROL +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGExtCorr_ACTION_CONTROL +#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//PCIE0PortGParityErr_ACTION_CONTROL +#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortASerr_ACTION_CONTROL +#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntFatal_ACTION_CONTROL +#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntNonFatal_ACTION_CONTROL +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAIntCorr_ACTION_CONTROL +#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtFatal_ACTION_CONTROL +#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtNonFatal_ACTION_CONTROL +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAExtCorr_ACTION_CONTROL +#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//NBIF1PortAParityErr_ACTION_CONTROL +#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0 +#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1 +#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3 +#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4 +#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L +#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L +#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L +#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L +//SYNCFLOOD_STATUS +#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0 +#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1 +#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2 +#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4 +#define SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT 0x5 +#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L +#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L +#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L +#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L +#define SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK 0x00000020L +//NMI_STATUS +#define NMI_STATUS__NMIFromPin__SHIFT 0x0 +#define NMI_STATUS__NMIFromPin_MASK 0x00000001L +//POISON_ACTION_CONTROL +#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT 0x0 +#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT 0x1 +#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT 0x3 +#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT 0x4 +#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT 0x8 +#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT 0x9 +#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT 0xb +#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT 0xc +#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT 0x10 +#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT 0x11 +#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT 0x13 +#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT 0x14 +#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK 0x00000001L +#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK 0x00000006L +#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK 0x00000008L +#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK 0x00000010L +#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK 0x00000100L +#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK 0x00000600L +#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK 0x00000800L +#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK 0x00001000L +#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK 0x00010000L +#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK 0x00060000L +#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK 0x00080000L +#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK 0x00100000L +//INTERNAL_POISON_STATUS +#define INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT 0x0 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT 0x1 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT 0x2 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT 0x3 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT 0x4 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT 0x5 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT 0x6 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT 0x7 +#define INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK 0x00000001L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK 0x00000002L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK 0x00000004L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK 0x00000008L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK 0x00000010L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK 0x00000020L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK 0x00000040L +#define INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK 0x00000080L +//INTERNAL_POISON_MASK +#define INTERNAL_POISON_MASK__IntPoisonMask__SHIFT 0x0 +#define INTERNAL_POISON_MASK__IntPoisonMask_MASK 0x000000FFL +//EGRESS_POISON_STATUS_LO +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19 +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L +#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L +//EGRESS_POISON_STATUS_HI +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19 +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L +#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L +//EGRESS_POISON_MASK_LO +#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0 +#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL +//EGRESS_POISON_MASK_HI +#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0 +#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL +//EGRESS_POISON_SEVERITY_DOWN +#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0 +#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL +//EGRESS_POISON_SEVERITY_UPPER +#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0 +#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL +//APML_STATUS +#define APML_STATUS__APML_Corr__SHIFT 0x0 +#define APML_STATUS__APML_NonFatal__SHIFT 0x1 +#define APML_STATUS__APML_Fatal__SHIFT 0x2 +#define APML_STATUS__APML_Serr__SHIFT 0x3 +#define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4 +#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5 +#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6 +#define APML_STATUS__APML_Corr_MASK 0x00000001L +#define APML_STATUS__APML_NonFatal_MASK 0x00000002L +#define APML_STATUS__APML_Fatal_MASK 0x00000004L +#define APML_STATUS__APML_Serr_MASK 0x00000008L +#define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L +#define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L +#define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L +//APML_CONTROL +#define APML_CONTROL__APML_NMI_En__SHIFT 0x0 +#define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1 +#define APML_CONTROL__APML_OutputDis__SHIFT 0x8 +#define APML_CONTROL__APML_NMI_En_MASK 0x00000001L +#define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L +#define APML_CONTROL__APML_OutputDis_MASK 0x00000100L +//APML_TRIGGER +#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0 +#define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +//NB_PCIE0DEVINDCFG0_STEERING_CNTL +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +//NB_PCIE0DEVINDCFG1_STEERING_CNTL +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG1_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +//NB_PCIE0DEVINDCFG2_STEERING_CNTL +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG2_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +//NB_PCIE0DEVINDCFG3_STEERING_CNTL +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG3_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +//NB_PCIE0DEVINDCFG4_STEERING_CNTL +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG4_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +//NB_PCIE0DEVINDCFG5_STEERING_CNTL +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG5_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +//NB_PCIE0DEVINDCFG6_STEERING_CNTL +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_PCIE0DEVINDCFG6_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +//NB_NBIF1DEVINDCFG0_STEERING_CNTL +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_NBIF1DEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +//NB_INTSBDEVINDCFG0_STEERING_CNTL +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering__SHIFT 0x0 +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue__SHIFT 0x8 +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__ForceSteering_MASK 0x00000001L +#define NB_INTSBDEVINDCFG0_STEERING_CNTL__SteeringValue_MASK 0x0000FF00L + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION__RC_SMN_INDEX_EXTENSION_MASK 0x000000FFL +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX__RC_SMN_INDEX_MASK 0xFFFFFFFFL +//NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA__SHIFT 0x0 +#define NB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA__RC_SMN_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_iommu_l2a_l2acfg +//L2_PERF_CNTL_0 +#define L2_PERF_CNTL_0__L2PerfEvent0__SHIFT 0x0 +#define L2_PERF_CNTL_0__L2PerfEvent1__SHIFT 0x8 +#define L2_PERF_CNTL_0__L2PerfCountUpper0__SHIFT 0x10 +#define L2_PERF_CNTL_0__L2PerfCountUpper1__SHIFT 0x18 +#define L2_PERF_CNTL_0__L2PerfEvent0_MASK 0x000000FFL +#define L2_PERF_CNTL_0__L2PerfEvent1_MASK 0x0000FF00L +#define L2_PERF_CNTL_0__L2PerfCountUpper0_MASK 0x00FF0000L +#define L2_PERF_CNTL_0__L2PerfCountUpper1_MASK 0xFF000000L +//L2_PERF_COUNT_0 +#define L2_PERF_COUNT_0__L2PerfCount0__SHIFT 0x0 +#define L2_PERF_COUNT_0__L2PerfCount0_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_1 +#define L2_PERF_COUNT_1__L2PerfCount1__SHIFT 0x0 +#define L2_PERF_COUNT_1__L2PerfCount1_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_1 +#define L2_PERF_CNTL_1__L2PerfEvent2__SHIFT 0x0 +#define L2_PERF_CNTL_1__L2PerfEvent3__SHIFT 0x8 +#define L2_PERF_CNTL_1__L2PerfCountUpper2__SHIFT 0x10 +#define L2_PERF_CNTL_1__L2PerfCountUpper3__SHIFT 0x18 +#define L2_PERF_CNTL_1__L2PerfEvent2_MASK 0x000000FFL +#define L2_PERF_CNTL_1__L2PerfEvent3_MASK 0x0000FF00L +#define L2_PERF_CNTL_1__L2PerfCountUpper2_MASK 0x00FF0000L +#define L2_PERF_CNTL_1__L2PerfCountUpper3_MASK 0xFF000000L +//L2_PERF_COUNT_2 +#define L2_PERF_COUNT_2__L2PerfCount2__SHIFT 0x0 +#define L2_PERF_COUNT_2__L2PerfCount2_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_3 +#define L2_PERF_COUNT_3__L2PerfCount3__SHIFT 0x0 +#define L2_PERF_COUNT_3__L2PerfCount3_MASK 0xFFFFFFFFL +//L2_STATUS_0 +#define L2_STATUS_0__L2STATUS0__SHIFT 0x0 +#define L2_STATUS_0__L2STATUS0_MASK 0xFFFFFFFFL +//L2_CONTROL_0 +#define L2_CONTROL_0__AllowL1CacheVZero__SHIFT 0x1 +#define L2_CONTROL_0__AllowL1CacheATSRsp__SHIFT 0x2 +#define L2_CONTROL_0__DTCHitVZeroOrIVZero__SHIFT 0x3 +#define L2_CONTROL_0__SIDEPTEOnUntransExcl__SHIFT 0xa +#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl__SHIFT 0xb +#define L2_CONTROL_0__AllowL1CacheLargePagemode0__SHIFT 0x13 +#define L2_CONTROL_0__IFifoBurstLength__SHIFT 0x14 +#define L2_CONTROL_0__IFifoClientPriority__SHIFT 0x18 +#define L2_CONTROL_0__AllowL1CacheVZero_MASK 0x00000002L +#define L2_CONTROL_0__AllowL1CacheATSRsp_MASK 0x00000004L +#define L2_CONTROL_0__DTCHitVZeroOrIVZero_MASK 0x00000008L +#define L2_CONTROL_0__SIDEPTEOnUntransExcl_MASK 0x00000400L +#define L2_CONTROL_0__SIDEPTEOnAddrTransExcl_MASK 0x00000800L +#define L2_CONTROL_0__AllowL1CacheLargePagemode0_MASK 0x00080000L +#define L2_CONTROL_0__IFifoBurstLength_MASK 0x00F00000L +#define L2_CONTROL_0__IFifoClientPriority_MASK 0xFF000000L +//L2_CONTROL_1 +#define L2_CONTROL_1__SeqInvBurstLimitInv__SHIFT 0x0 +#define L2_CONTROL_1__SeqInvBurstLimitL2Req__SHIFT 0x8 +#define L2_CONTROL_1__SeqInvBurstLimitEn__SHIFT 0x10 +#define L2_CONTROL_1__DBUSDis__SHIFT 0x11 +#define L2_CONTROL_1__PerfThreshold__SHIFT 0x18 +#define L2_CONTROL_1__SeqInvBurstLimitInv_MASK 0x000000FFL +#define L2_CONTROL_1__SeqInvBurstLimitL2Req_MASK 0x0000FF00L +#define L2_CONTROL_1__SeqInvBurstLimitEn_MASK 0x00010000L +#define L2_CONTROL_1__DBUSDis_MASK 0x00020000L +#define L2_CONTROL_1__PerfThreshold_MASK 0xFF000000L +//L2_DTC_CONTROL +#define L2_DTC_CONTROL__DTCLRUUpdatePri__SHIFT 0x3 +#define L2_DTC_CONTROL__DTCParityEn__SHIFT 0x4 +#define L2_DTC_CONTROL__DTCInvalidationSel__SHIFT 0x8 +#define L2_DTC_CONTROL__DTCSoftInvalidate__SHIFT 0xa +#define L2_DTC_CONTROL__DTCBypass__SHIFT 0xd +#define L2_DTC_CONTROL__DTCParitySupport__SHIFT 0xf +#define L2_DTC_CONTROL__DTCWays__SHIFT 0x10 +#define L2_DTC_CONTROL__DTCEntries__SHIFT 0x1c +#define L2_DTC_CONTROL__DTCLRUUpdatePri_MASK 0x00000008L +#define L2_DTC_CONTROL__DTCParityEn_MASK 0x00000010L +#define L2_DTC_CONTROL__DTCInvalidationSel_MASK 0x00000300L +#define L2_DTC_CONTROL__DTCSoftInvalidate_MASK 0x00000400L +#define L2_DTC_CONTROL__DTCBypass_MASK 0x00002000L +#define L2_DTC_CONTROL__DTCParitySupport_MASK 0x00008000L +#define L2_DTC_CONTROL__DTCWays_MASK 0x00FF0000L +#define L2_DTC_CONTROL__DTCEntries_MASK 0xF0000000L +//L2_DTC_HASH_CONTROL +#define L2_DTC_HASH_CONTROL__DTCAddressMask__SHIFT 0x10 +#define L2_DTC_HASH_CONTROL__DTCAddressMask_MASK 0xFFFF0000L +//L2_DTC_WAY_CONTROL +#define L2_DTC_WAY_CONTROL__DTCWayDisable__SHIFT 0x0 +#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable__SHIFT 0x10 +#define L2_DTC_WAY_CONTROL__DTCWayDisable_MASK 0x0000FFFFL +#define L2_DTC_WAY_CONTROL__DTCWayAccessDisable_MASK 0xFFFF0000L +//L2_ITC_CONTROL +#define L2_ITC_CONTROL__ITCLRUUpdatePri__SHIFT 0x3 +#define L2_ITC_CONTROL__ITCParityEn__SHIFT 0x4 +#define L2_ITC_CONTROL__ITCInvalidationSel__SHIFT 0x8 +#define L2_ITC_CONTROL__ITCSoftInvalidate__SHIFT 0xa +#define L2_ITC_CONTROL__ITCBypass__SHIFT 0xd +#define L2_ITC_CONTROL__ITCParitySupport__SHIFT 0xf +#define L2_ITC_CONTROL__ITCWays__SHIFT 0x10 +#define L2_ITC_CONTROL__ITCEntries__SHIFT 0x1c +#define L2_ITC_CONTROL__ITCLRUUpdatePri_MASK 0x00000008L +#define L2_ITC_CONTROL__ITCParityEn_MASK 0x00000010L +#define L2_ITC_CONTROL__ITCInvalidationSel_MASK 0x00000300L +#define L2_ITC_CONTROL__ITCSoftInvalidate_MASK 0x00000400L +#define L2_ITC_CONTROL__ITCBypass_MASK 0x00002000L +#define L2_ITC_CONTROL__ITCParitySupport_MASK 0x00008000L +#define L2_ITC_CONTROL__ITCWays_MASK 0x00FF0000L +#define L2_ITC_CONTROL__ITCEntries_MASK 0xF0000000L +//L2_ITC_HASH_CONTROL +#define L2_ITC_HASH_CONTROL__ITCAddressMask__SHIFT 0x10 +#define L2_ITC_HASH_CONTROL__ITCAddressMask_MASK 0xFFFF0000L +//L2_ITC_WAY_CONTROL +#define L2_ITC_WAY_CONTROL__ITCWayDisable__SHIFT 0x0 +#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable__SHIFT 0x10 +#define L2_ITC_WAY_CONTROL__ITCWayDisable_MASK 0x0000FFFFL +#define L2_ITC_WAY_CONTROL__ITCWayAccessDisable_MASK 0xFFFF0000L +//L2_PTC_A_CONTROL +#define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate__SHIFT 0x1 +#define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate__SHIFT 0x2 +#define L2_PTC_A_CONTROL__PTCALRUUpdatePri__SHIFT 0x3 +#define L2_PTC_A_CONTROL__PTCAParityEn__SHIFT 0x4 +#define L2_PTC_A_CONTROL__PTCAInvalidationSel__SHIFT 0x8 +#define L2_PTC_A_CONTROL__PTCASoftInvalidate__SHIFT 0xa +#define L2_PTC_A_CONTROL__PTCA2MMode__SHIFT 0xb +#define L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages__SHIFT 0xc +#define L2_PTC_A_CONTROL__PTCABypass__SHIFT 0xd +#define L2_PTC_A_CONTROL__PTCAFastInvalidateGuest__SHIFT 0xe +#define L2_PTC_A_CONTROL__PTCAParitySupport__SHIFT 0xf +#define L2_PTC_A_CONTROL__PTCAWays__SHIFT 0x10 +#define L2_PTC_A_CONTROL__PTCAEntries__SHIFT 0x1c +#define L2_PTC_A_CONTROL__PTCAStoreFinalATSeperate_MASK 0x00000002L +#define L2_PTC_A_CONTROL__PTCAStorePartialATSeperate_MASK 0x00000004L +#define L2_PTC_A_CONTROL__PTCALRUUpdatePri_MASK 0x00000008L +#define L2_PTC_A_CONTROL__PTCAParityEn_MASK 0x00000010L +#define L2_PTC_A_CONTROL__PTCAInvalidationSel_MASK 0x00000300L +#define L2_PTC_A_CONTROL__PTCASoftInvalidate_MASK 0x00000400L +#define L2_PTC_A_CONTROL__PTCA2MMode_MASK 0x00000800L +#define L2_PTC_A_CONTROL__PCTA_Inv_Overlapping_Pages_MASK 0x00001000L +#define L2_PTC_A_CONTROL__PTCABypass_MASK 0x00002000L +#define L2_PTC_A_CONTROL__PTCAFastInvalidateGuest_MASK 0x00004000L +#define L2_PTC_A_CONTROL__PTCAParitySupport_MASK 0x00008000L +#define L2_PTC_A_CONTROL__PTCAWays_MASK 0x00FF0000L +#define L2_PTC_A_CONTROL__PTCAEntries_MASK 0xF0000000L +//L2_PTC_A_HASH_CONTROL +#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask__SHIFT 0x10 +#define L2_PTC_A_HASH_CONTROL__PTCAAddressMask_MASK 0xFFFF0000L +//L2_PTC_A_WAY_CONTROL +#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable__SHIFT 0x0 +#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable__SHIFT 0x10 +#define L2_PTC_A_WAY_CONTROL__PTCAWayDisable_MASK 0x0000FFFFL +#define L2_PTC_A_WAY_CONTROL__PTCAWayAccessDisable_MASK 0xFFFF0000L +//L2A_UPDATE_FILTER_CNTL +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass__SHIFT 0x0 +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency__SHIFT 0x1 +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_Bypass_MASK 0x00000001L +#define L2A_UPDATE_FILTER_CNTL__L2a_Update_Filter_RdLatency_MASK 0x0000001EL +//L2_ERR_RULE_CONTROL_3 +#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3__SHIFT 0x4 +#define L2_ERR_RULE_CONTROL_3__ERRRuleLock1_MASK 0x00000001L +#define L2_ERR_RULE_CONTROL_3__ERRRuleDisable3_MASK 0xFFFFFFF0L +//L2_ERR_RULE_CONTROL_4 +#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_4__ERRRuleDisable4_MASK 0xFFFFFFFFL +//L2_ERR_RULE_CONTROL_5 +#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_5__ERRRuleDisable5_MASK 0xFFFFFFFFL +//L2_L2A_CK_GATE_CONTROL +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable__SHIFT 0x0 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable__SHIFT 0x1 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable__SHIFT 0x2 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable__SHIFT 0x3 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength__SHIFT 0x10 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop__SHIFT 0x12 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis__SHIFT 0x14 +#define L2_L2A_CK_GATE_CONTROL__Reserved__SHIFT 0x15 +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ARegsDisable_MASK 0x00000001L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ADynamicDisable_MASK 0x00000002L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ACacheDisable_MASK 0x00000004L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APerfDisable_MASK 0x00000008L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2ALength_MASK 0x00030000L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2AStop_MASK 0x000C0000L +#define L2_L2A_CK_GATE_CONTROL__CKGateL2APortClkDis_MASK 0x00100000L +#define L2_L2A_CK_GATE_CONTROL__Reserved_MASK 0xFFE00000L +//L2_L2A_PGSIZE_CONTROL +#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE__SHIFT 0x0 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE__SHIFT 0x8 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE__SHIFT 0x11 +#define L2_L2A_PGSIZE_CONTROL__L2AREG_GST_PGSIZE_MASK 0x0000007FL +#define L2_L2A_PGSIZE_CONTROL__L2AREG_HOST_PGSIZE_MASK 0x00007F00L +#define L2_L2A_PGSIZE_CONTROL__L2AREG_PTCSCAN_MODE_MASK 0x000E0000L +//L2_PWRGATE_CNTRL_REG_0 +#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres__SHIFT 0x0 +#define L2_PWRGATE_CNTRL_REG_0__IP_PG_thres_MASK 0xFFFFFFFFL +//L2_PWRGATE_CNTRL_REG_3 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en__SHIFT 0x0 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy__SHIFT 0x1 +#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS__SHIFT 0x2 +#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN__SHIFT 0x3 +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_en_MASK 0x00000001L +#define L2_PWRGATE_CNTRL_REG_3__IP_PG_busy_MASK 0x00000002L +#define L2_PWRGATE_CNTRL_REG_3__L2_PG_STATUS_MASK 0x00000004L +#define L2_PWRGATE_CNTRL_REG_3__CFG_FW_PG_EXIT_EN_MASK 0x00000018L +//L2_ECO_CNTRL_0 +#define L2_ECO_CNTRL_0__L2_ECO_0__SHIFT 0x0 +#define L2_ECO_CNTRL_0__L2_ECO_0_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_iohub_iommu_l2indx_l2indxcfg +//L2_STATUS_1 +#define L2_STATUS_1__L2STATUS1__SHIFT 0x0 +#define L2_STATUS_1__L2STATUS1_MASK 0xFFFFFFFFL +//L2_SB_LOCATION +#define L2_SB_LOCATION__SBlocated_Port__SHIFT 0x0 +#define L2_SB_LOCATION__SBlocated_Core__SHIFT 0x10 +#define L2_SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL +#define L2_SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L +//L2_CONTROL_5 +#define L2_CONTROL_5__QueueArbFBPri__SHIFT 0x0 +#define L2_CONTROL_5__FC1Dis__SHIFT 0x2 +#define L2_CONTROL_5__DTCUpdateVOneIVZero__SHIFT 0x3 +#define L2_CONTROL_5__DTCUpdateVZeroIVOne__SHIFT 0x4 +#define L2_CONTROL_5__FC3Dis__SHIFT 0x6 +#define L2_CONTROL_5__ForceTWonVCQoS__SHIFT 0xb +#define L2_CONTROL_5__GST_partial_ptc_cntrl__SHIFT 0xc +#define L2_CONTROL_5__STORE_PDPE_QOS_PTC__SHIFT 0x14 +#define L2_CONTROL_5__DTCUpdatePri__SHIFT 0x19 +#define L2_CONTROL_5__L2B_L2A_v1_trans_credits__SHIFT 0x1a +#define L2_CONTROL_5__QueueArbFBPri_MASK 0x00000001L +#define L2_CONTROL_5__FC1Dis_MASK 0x00000004L +#define L2_CONTROL_5__DTCUpdateVOneIVZero_MASK 0x00000008L +#define L2_CONTROL_5__DTCUpdateVZeroIVOne_MASK 0x00000010L +#define L2_CONTROL_5__FC3Dis_MASK 0x00000040L +#define L2_CONTROL_5__ForceTWonVCQoS_MASK 0x00000800L +#define L2_CONTROL_5__GST_partial_ptc_cntrl_MASK 0x0007F000L +#define L2_CONTROL_5__STORE_PDPE_QOS_PTC_MASK 0x00100000L +#define L2_CONTROL_5__DTCUpdatePri_MASK 0x02000000L +#define L2_CONTROL_5__L2B_L2A_v1_trans_credits_MASK 0xFC000000L +//L2_CONTROL_6 +#define L2_CONTROL_6__SeqInvBurstLimitInv__SHIFT 0x0 +#define L2_CONTROL_6__SeqInvBurstLimitPDCReq__SHIFT 0x8 +#define L2_CONTROL_6__SeqInvBurstLimitEn__SHIFT 0x10 +#define L2_CONTROL_6__Perf2Threshold__SHIFT 0x18 +#define L2_CONTROL_6__SeqInvBurstLimitInv_MASK 0x000000FFL +#define L2_CONTROL_6__SeqInvBurstLimitPDCReq_MASK 0x0000FF00L +#define L2_CONTROL_6__SeqInvBurstLimitEn_MASK 0x00010000L +#define L2_CONTROL_6__Perf2Threshold_MASK 0xFF000000L +//L2_PDC_CONTROL +#define L2_PDC_CONTROL__PDCLRUUpdatePri__SHIFT 0x3 +#define L2_PDC_CONTROL__PDCParityEn__SHIFT 0x4 +#define L2_PDC_CONTROL__PDCInvalidationSel__SHIFT 0x8 +#define L2_PDC_CONTROL__PDCSoftInvalidate__SHIFT 0xa +#define L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages__SHIFT 0xb +#define L2_PDC_CONTROL__PDCSearchDirection__SHIFT 0xc +#define L2_PDC_CONTROL__PDCBypass__SHIFT 0xd +#define L2_PDC_CONTROL__PDCModeLookupFix__SHIFT 0xe +#define L2_PDC_CONTROL__PDCParitySupport__SHIFT 0xf +#define L2_PDC_CONTROL__PDCWays__SHIFT 0x10 +#define L2_PDC_CONTROL__PDCEntries__SHIFT 0x1c +#define L2_PDC_CONTROL__PDCLRUUpdatePri_MASK 0x00000008L +#define L2_PDC_CONTROL__PDCParityEn_MASK 0x00000010L +#define L2_PDC_CONTROL__PDCInvalidationSel_MASK 0x00000300L +#define L2_PDC_CONTROL__PDCSoftInvalidate_MASK 0x00000400L +#define L2_PDC_CONTROL__PDC_Inv_Overlapping_Pages_MASK 0x00000800L +#define L2_PDC_CONTROL__PDCSearchDirection_MASK 0x00001000L +#define L2_PDC_CONTROL__PDCBypass_MASK 0x00002000L +#define L2_PDC_CONTROL__PDCModeLookupFix_MASK 0x00004000L +#define L2_PDC_CONTROL__PDCParitySupport_MASK 0x00008000L +#define L2_PDC_CONTROL__PDCWays_MASK 0x00FF0000L +#define L2_PDC_CONTROL__PDCEntries_MASK 0xF0000000L +//L2_PDC_HASH_CONTROL +#define L2_PDC_HASH_CONTROL__PDCAddressMask__SHIFT 0x10 +#define L2_PDC_HASH_CONTROL__PDCAddressMask_MASK 0xFFFF0000L +//L2_PDC_WAY_CONTROL +#define L2_PDC_WAY_CONTROL__PDCWayDisable__SHIFT 0x0 +#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable__SHIFT 0x10 +#define L2_PDC_WAY_CONTROL__PDCWayDisable_MASK 0x0000FFFFL +#define L2_PDC_WAY_CONTROL__PDCWayAccessDisable_MASK 0xFFFF0000L +//L2B_UPDATE_FILTER_CNTL +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass__SHIFT 0x0 +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency__SHIFT 0x1 +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_Bypass_MASK 0x00000001L +#define L2B_UPDATE_FILTER_CNTL__L2b_Update_Filter_RdLatency_MASK 0x0000001EL +//L2_TW_CONTROL +#define L2_TW_CONTROL__RESERVED__SHIFT 0x0 +#define L2_TW_CONTROL__TWForceCoherent__SHIFT 0x6 +#define L2_TW_CONTROL__TWPrefetchEn__SHIFT 0x8 +#define L2_TW_CONTROL__TWPrefetchOnly4KDis__SHIFT 0x9 +#define L2_TW_CONTROL__TWPTEOnUntransExcl__SHIFT 0xa +#define L2_TW_CONTROL__TWPTEOnAddrTransExcl__SHIFT 0xb +#define L2_TW_CONTROL__TWPrefetchRange__SHIFT 0xc +#define L2_TW_CONTROL__TWFilter_Dis__SHIFT 0x10 +#define L2_TW_CONTROL__TWFilter_64B_Dis__SHIFT 0x11 +#define L2_TW_CONTROL__TWContWalkOnPErrDis__SHIFT 0x12 +#define L2_TW_CONTROL__TWSetAccessBit_Dis__SHIFT 0x13 +#define L2_TW_CONTROL__TWClearAPBit_Dis__SHIFT 0x14 +#define L2_TW_CONTROL__TWCacheNestedPTE__SHIFT 0x19 +#define L2_TW_CONTROL__RESERVED_MASK 0x0000003FL +#define L2_TW_CONTROL__TWForceCoherent_MASK 0x00000040L +#define L2_TW_CONTROL__TWPrefetchEn_MASK 0x00000100L +#define L2_TW_CONTROL__TWPrefetchOnly4KDis_MASK 0x00000200L +#define L2_TW_CONTROL__TWPTEOnUntransExcl_MASK 0x00000400L +#define L2_TW_CONTROL__TWPTEOnAddrTransExcl_MASK 0x00000800L +#define L2_TW_CONTROL__TWPrefetchRange_MASK 0x00007000L +#define L2_TW_CONTROL__TWFilter_Dis_MASK 0x00010000L +#define L2_TW_CONTROL__TWFilter_64B_Dis_MASK 0x00020000L +#define L2_TW_CONTROL__TWContWalkOnPErrDis_MASK 0x00040000L +#define L2_TW_CONTROL__TWSetAccessBit_Dis_MASK 0x00080000L +#define L2_TW_CONTROL__TWClearAPBit_Dis_MASK 0x00100000L +#define L2_TW_CONTROL__TWCacheNestedPTE_MASK 0x02000000L +//L2_CP_CONTROL +#define L2_CP_CONTROL__CPPrefetchDis__SHIFT 0x0 +#define L2_CP_CONTROL__CPFlushOnWait__SHIFT 0x1 +#define L2_CP_CONTROL__CPFlushOnInv__SHIFT 0x2 +#define L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl__SHIFT 0x3 +#define L2_CP_CONTROL__CPForceReqPassPW__SHIFT 0x4 +#define L2_CP_CONTROL__CPForceOneOutstandingCommand__SHIFT 0x5 +#define L2_CP_CONTROL__CPRdDelay__SHIFT 0x10 +#define L2_CP_CONTROL__CPPrefetchDis_MASK 0x00000001L +#define L2_CP_CONTROL__CPFlushOnWait_MASK 0x00000002L +#define L2_CP_CONTROL__CPFlushOnInv_MASK 0x00000004L +#define L2_CP_CONTROL__CPStallCmdErrForIOTLBCmpl_MASK 0x00000008L +#define L2_CP_CONTROL__CPForceReqPassPW_MASK 0x00000010L +#define L2_CP_CONTROL__CPForceOneOutstandingCommand_MASK 0x00000020L +#define L2_CP_CONTROL__CPRdDelay_MASK 0xFFFF0000L +//L2_CP_CONTROL_1 +#define L2_CP_CONTROL_1__CPL1Off__SHIFT 0x0 +#define L2_CP_CONTROL_1__Reserved__SHIFT 0x10 +#define L2_CP_CONTROL_1__CPL1Off_MASK 0x0000FFFFL +#define L2_CP_CONTROL_1__Reserved_MASK 0xFFFF0000L +//L2_TW_CONTROL_1 +#define L2_TW_CONTROL_1__TWTraceEn__SHIFT 0x0 +#define L2_TW_CONTROL_1__TWTraceNoWrap__SHIFT 0x1 +#define L2_TW_CONTROL_1__TWTraceForceDisable__SHIFT 0x2 +#define L2_TW_CONTROL_1__TWTraceMask__SHIFT 0xf +#define L2_TW_CONTROL_1__TWTraceEn_MASK 0x00000001L +#define L2_TW_CONTROL_1__TWTraceNoWrap_MASK 0x00000002L +#define L2_TW_CONTROL_1__TWTraceForceDisable_MASK 0x00000004L +#define L2_TW_CONTROL_1__TWTraceMask_MASK 0xFFFF8000L +//L2_TW_CONTROL_2 +#define L2_TW_CONTROL_2__TWTraceAddrLo__SHIFT 0xc +#define L2_TW_CONTROL_2__TWTraceAddrLo_MASK 0xFFFFF000L +//L2_TW_CONTROL_3 +#define L2_TW_CONTROL_3__TWTraceAddrHi__SHIFT 0x0 +#define L2_TW_CONTROL_3__TWTraceAddrHi_MASK 0xFFFFFFFFL +//L2_CREDIT_CONTROL_0 +#define L2_CREDIT_CONTROL_0__FC1Credits__SHIFT 0x0 +#define L2_CREDIT_CONTROL_0__FC1Override__SHIFT 0x7 +#define L2_CREDIT_CONTROL_0__FC3Credits__SHIFT 0xf +#define L2_CREDIT_CONTROL_0__FC3Override__SHIFT 0x15 +#define L2_CREDIT_CONTROL_0__FC1Credits_MASK 0x0000007FL +#define L2_CREDIT_CONTROL_0__FC1Override_MASK 0x00000080L +#define L2_CREDIT_CONTROL_0__FC3Credits_MASK 0x001F8000L +#define L2_CREDIT_CONTROL_0__FC3Override_MASK 0x00200000L +//L2_CREDIT_CONTROL_1 +#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits__SHIFT 0x10 +#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits__SHIFT 0x14 +#define L2_CREDIT_CONTROL_1__CP_PREFETCH_credits_MASK 0x000F0000L +#define L2_CREDIT_CONTROL_1__PPR_MCIF_credits_MASK 0x00F00000L +//L2_ERR_RULE_CONTROL_0 +#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0__SHIFT 0x1 +#define L2_ERR_RULE_CONTROL_0__ERRRuleLock0_MASK 0x00000001L +#define L2_ERR_RULE_CONTROL_0__ERRRuleDisable0_MASK 0xFFFFFFFEL +//L2_ERR_RULE_CONTROL_1 +#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_1__ERRRuleDisable1_MASK 0xFFFFFFFFL +//L2_ERR_RULE_CONTROL_2 +#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2__SHIFT 0x0 +#define L2_ERR_RULE_CONTROL_2__ERRRuleDisable2_MASK 0xFFFFFFFFL +//L2_L2B_CK_GATE_CONTROL +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable__SHIFT 0x0 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable__SHIFT 0x1 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable__SHIFT 0x2 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable__SHIFT 0x3 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable__SHIFT 0x4 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable__SHIFT 0x5 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis__SHIFT 0x6 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength__SHIFT 0x10 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop__SHIFT 0x12 +#define L2_L2B_CK_GATE_CONTROL__Reserved__SHIFT 0x14 +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BRegsDisable_MASK 0x00000001L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BDynamicDisable_MASK 0x00000002L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BMiscDisable_MASK 0x00000004L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BCacheDisable_MASK 0x00000008L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BAPCDisable_MASK 0x00000010L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPerfDisable_MASK 0x00000020L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BPortClkDis_MASK 0x00000040L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BLength_MASK 0x00030000L +#define L2_L2B_CK_GATE_CONTROL__CKGateL2BStop_MASK 0x000C0000L +#define L2_L2B_CK_GATE_CONTROL__Reserved_MASK 0xFFF00000L +//PPR_CONTROL +#define PPR_CONTROL__PPR_IntTimeDelay__SHIFT 0x0 +#define PPR_CONTROL__PPR_IntReqDelay__SHIFT 0x8 +#define PPR_CONTROL__PPR_IntCoallesce_En__SHIFT 0x10 +#define PPR_CONTROL__PPR_IntTimeDelay_MASK 0x000000FFL +#define PPR_CONTROL__PPR_IntReqDelay_MASK 0x0000FF00L +#define PPR_CONTROL__PPR_IntCoallesce_En_MASK 0x00010000L +//L2_L2B_PGSIZE_CONTROL +#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE__SHIFT 0x0 +#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE__SHIFT 0x8 +#define L2_L2B_PGSIZE_CONTROL__L2BREG_GST_PGSIZE_MASK 0x0000007FL +#define L2_L2B_PGSIZE_CONTROL__L2BREG_HOST_PGSIZE_MASK 0x00007F00L +//L2_PERF_CNTL_2 +#define L2_PERF_CNTL_2__L2PerfEvent4__SHIFT 0x0 +#define L2_PERF_CNTL_2__L2PerfEvent5__SHIFT 0x8 +#define L2_PERF_CNTL_2__L2PerfCountUpper4__SHIFT 0x10 +#define L2_PERF_CNTL_2__L2PerfCountUpper5__SHIFT 0x18 +#define L2_PERF_CNTL_2__L2PerfEvent4_MASK 0x000000FFL +#define L2_PERF_CNTL_2__L2PerfEvent5_MASK 0x0000FF00L +#define L2_PERF_CNTL_2__L2PerfCountUpper4_MASK 0x00FF0000L +#define L2_PERF_CNTL_2__L2PerfCountUpper5_MASK 0xFF000000L +//L2_PERF_COUNT_4 +#define L2_PERF_COUNT_4__L2PerfCount4__SHIFT 0x0 +#define L2_PERF_COUNT_4__L2PerfCount4_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_5 +#define L2_PERF_COUNT_5__L2PerfCount5__SHIFT 0x0 +#define L2_PERF_COUNT_5__L2PerfCount5_MASK 0xFFFFFFFFL +//L2_PERF_CNTL_3 +#define L2_PERF_CNTL_3__L2PerfEvent6__SHIFT 0x0 +#define L2_PERF_CNTL_3__L2PerfEvent7__SHIFT 0x8 +#define L2_PERF_CNTL_3__L2PerfCountUpper6__SHIFT 0x10 +#define L2_PERF_CNTL_3__L2PerfCountUpper7__SHIFT 0x18 +#define L2_PERF_CNTL_3__L2PerfEvent6_MASK 0x000000FFL +#define L2_PERF_CNTL_3__L2PerfEvent7_MASK 0x0000FF00L +#define L2_PERF_CNTL_3__L2PerfCountUpper6_MASK 0x00FF0000L +#define L2_PERF_CNTL_3__L2PerfCountUpper7_MASK 0xFF000000L +//L2_PERF_COUNT_6 +#define L2_PERF_COUNT_6__L2PerfCount6__SHIFT 0x0 +#define L2_PERF_COUNT_6__L2PerfCount6_MASK 0xFFFFFFFFL +//L2_PERF_COUNT_7 +#define L2_PERF_COUNT_7__L2PerfCount7__SHIFT 0x0 +#define L2_PERF_COUNT_7__L2PerfCount7_MASK 0xFFFFFFFFL +//L2B_SDP_PARITY_ERROR_EN +#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN__SHIFT 0x0 +#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN__SHIFT 0x1 +#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN__SHIFT 0x2 +#define L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN__SHIFT 0x3 +#define L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN__SHIFT 0x4 +#define L2B_SDP_PARITY_ERROR_EN__DVM_PARITY_ERROR_EN_MASK 0x00000001L +#define L2B_SDP_PARITY_ERROR_EN__CP_PARITY_ERROR_EN_MASK 0x00000002L +#define L2B_SDP_PARITY_ERROR_EN__TWW_PARITY_ERROR_EN_MASK 0x00000004L +#define L2B_SDP_PARITY_ERROR_EN__VFMMIO_PARITY_ERROR_EN_MASK 0x00000008L +#define L2B_SDP_PARITY_ERROR_EN__MSG_PARITY_ERROR_EN_MASK 0x00000010L +//L2_ECO_CNTRL_1 +#define L2_ECO_CNTRL_1__L2_ECO_1__SHIFT 0x0 +#define L2_ECO_CNTRL_1__L2_ECO_1_MASK 0xFFFFFFFFL +//L2_CP_CONTROL_2 +#define L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV__SHIFT 0x0 +#define L2_CP_CONTROL_2__LEGACY_CWWB_PATH__SHIFT 0x1 +#define L2_CP_CONTROL_2__gstcp_always_refetch_v1__SHIFT 0x2 +#define L2_CP_CONTROL_2__inv_waitcmpl_mode__SHIFT 0x16 +#define L2_CP_CONTROL_2__inv_dvmsync_mode__SHIFT 0x18 +#define L2_CP_CONTROL_2__inv_pspflush_mode__SHIFT 0x1a +#define L2_CP_CONTROL_2__wqmask_propagation_latency__SHIFT 0x1c +#define L2_CP_CONTROL_2__OVERCONSTRAIN_CMD_WQ_ON_INV_MASK 0x00000001L +#define L2_CP_CONTROL_2__LEGACY_CWWB_PATH_MASK 0x00000002L +#define L2_CP_CONTROL_2__gstcp_always_refetch_v1_MASK 0x00000004L +#define L2_CP_CONTROL_2__inv_waitcmpl_mode_MASK 0x00C00000L +#define L2_CP_CONTROL_2__inv_dvmsync_mode_MASK 0x03000000L +#define L2_CP_CONTROL_2__inv_pspflush_mode_MASK 0x0C000000L +#define L2_CP_CONTROL_2__wqmask_propagation_latency_MASK 0xF0000000L +//L2_CP_CONTROL_3 +#define L2_CP_CONTROL_3__INV_CMD_PRIORITY__SHIFT 0x0 +#define L2_CP_CONTROL_3__WAIT_CMD_PRIORITY__SHIFT 0x4 +#define L2_CP_CONTROL_3__SYNC_CMD_PRIORITY__SHIFT 0x8 +#define L2_CP_CONTROL_3__PSP_CMD_PRIORITY__SHIFT 0xc +#define L2_CP_CONTROL_3__INV_CMD_PRIORITY_MASK 0x0000000FL +#define L2_CP_CONTROL_3__WAIT_CMD_PRIORITY_MASK 0x000000F0L +#define L2_CP_CONTROL_3__SYNC_CMD_PRIORITY_MASK 0x00000F00L +#define L2_CP_CONTROL_3__PSP_CMD_PRIORITY_MASK 0x0000F000L + + +// addressBlock: aid_nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +//FEATURES_ENABLE +#define FEATURES_ENABLE__Ioapic_id_ext_en__SHIFT 0x2 +#define FEATURES_ENABLE__Ioapic_sb_feature_en__SHIFT 0x4 +#define FEATURES_ENABLE__Ioapic_secondary_en__SHIFT 0x5 +#define FEATURES_ENABLE__Ioapic_processor_mode__SHIFT 0x8 +#define FEATURES_ENABLE__INTx_LevelOnlyMode__SHIFT 0x9 +#define FEATURES_ENABLE__Ioapic_id_ext_en_MASK 0x00000004L +#define FEATURES_ENABLE__Ioapic_sb_feature_en_MASK 0x00000010L +#define FEATURES_ENABLE__Ioapic_secondary_en_MASK 0x00000020L +#define FEATURES_ENABLE__Ioapic_processor_mode_MASK 0x00000100L +#define FEATURES_ENABLE__INTx_LevelOnlyMode_MASK 0x00000200L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +//BIF_CFG_DEV0_RC_VENDOR_ID +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_DEVICE_ID +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_COMMAND +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_RC_STATUS +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_REVISION_ID +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_RC_PROG_INTERFACE +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_RC_SUB_CLASS +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_BASE_CLASS +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_RC_CACHE_LINE +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_RC_LATENCY +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_RC_HEADER +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_RC_BIST +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_RC_BASE_ADDR_1 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_BASE_ADDR_2 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L +#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_IO_BASE_LIMIT +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L +//BIF_CFG_DEV0_RC_SECONDARY_STATUS +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_RC_MEM_BASE_LIMIT +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PREF_BASE_LIMIT +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PREF_BASE_UPPER +#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER +#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_CAP_PTR +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_RC_ROM_BASE_ADDR +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_RC_INTERRUPT_LINE +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_RC_INTERRUPT_PIN +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//IRQ_BRIDGE_CNTL +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8 +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9 +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb +#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L +#define IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L +#define IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L +#define IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L +#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L +#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L +#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L +#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L +#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L +#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L +#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L +//BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL +#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L +//BIF_CFG_DEV0_RC_PMI_CAP_LIST +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PMI_CAP +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK 0x0007L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L +#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L +#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L +#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L +//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_CAP +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_RC_DEVICE_CAP +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_RC_LINK_CAP +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_LINK_CNTL +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_RC_LINK_STATUS +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_RC_SLOT_CAP +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L +#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L +#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L +//BIF_CFG_DEV0_RC_SLOT_CNTL +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd +#define BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT 0xe +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L +#define BIF_CFG_DEV0_RC_SLOT_CNTL__INBAND_PD_DISABLE_MASK 0x4000L +//BIF_CFG_DEV0_RC_SLOT_STATUS +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L +#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L +//BIF_CFG_DEV0_RC_ROOT_CNTL +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L +//BIF_CFG_DEV0_RC_ROOT_CAP +#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L +//BIF_CFG_DEV0_RC_ROOT_STATUS +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L +//BIF_CFG_DEV0_RC_DEVICE_CAP2 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DEVICE_CNTL2 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_RC_DEVICE_STATUS2 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_LINK_CAP2 +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_RC_LINK_CNTL2 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_RC_LINK_STATUS2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_RC_SLOT_CAP2 +#define BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK 0x00000001L +//BIF_CFG_DEV0_RC_SLOT_CNTL2 +#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_SLOT_STATUS2 +#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_CAP_LIST +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_MSI_MSG_CNTL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_RC_SSID_CAP_LIST +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_RC_SSID_CAP +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL +//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L +//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK 0x00000180L +#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L +//BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK 0x0000FE00L +//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L +#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L +//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_PCIE_ACS_CAP +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L +//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT 0x7 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT 0xa +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT 0xc +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK 0x0080L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0300L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK 0x0C00L +#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK 0x1000L +//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L +//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL +#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L +//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_LINK_CAP_16GT +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_CNTL_16GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_RC_LINK_STATUS_16GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L +//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL +//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL +#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L +//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L +//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L +#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L +#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L +//BIF_CFG_DEV0_RC_LINK_CAP_32GT +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT 0xb +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK 0x00000400L +#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK 0x0000F800L +//BIF_CFG_DEV0_RC_LINK_CNTL_32GT +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK 0x00000700L +//BIF_CFG_DEV0_RC_LINK_STATUS_32GT +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT 0x0 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT 0x1 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT 0x2 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT 0x3 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT 0x4 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT 0x5 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT 0x6 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT 0x8 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT 0x9 +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT 0xa +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK 0x00000001L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK 0x00000002L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK 0x00000004L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK 0x00000008L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK 0x00000010L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK 0x00000020L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK 0x000000C0L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK 0x00000100L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK 0x00000200L +#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK 0x00000400L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_COMMAND +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_HEADER +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BIST +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_COMMAND +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_HEADER +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BIST +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_COMMAND +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_HEADER +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BIST +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_COMMAND +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_HEADER +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BIST +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_COMMAND +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_HEADER +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BIST +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_COMMAND +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_HEADER +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BIST +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_COMMAND +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_HEADER +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BIST +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_COMMAND +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK 0x0600L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L +//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_HEADER +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK 0x7FL +#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BIST +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK 0x0FL +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK 0x40L +#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK 0x80L +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L +//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK 0x0000000EL +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK 0x000000F0L +#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFF800L +//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK 0xFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK 0x0003L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK 0x2000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK 0x0000FE00L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L +//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L +#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L +#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK 0x00000020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK 0x00000040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT 0x7 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK 0x0080L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK 0x001FL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L +//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L +#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF0_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF0_MM_DATA +#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF1_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF1_MM_DATA +#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF2_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF2_MM_DATA +#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF3_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF3_MM_DATA +#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF4_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF4_MM_DATA +#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF5_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF5_MM_DATA +#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF6_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF6_MM_DATA +#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L +//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L +//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L +#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS +#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L +//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L +//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L +#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +//BIF_BX_DEV0_EPF0_VF7_MM_INDEX +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT 0x1f +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK 0x80000000L +//BIF_BX_DEV0_EPF0_VF7_MM_DATA +#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL +//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L +//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL +//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L +//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L +#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L + + +#endif |