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authorEvan Quan <evan.quan@amd.com>2020-08-07 11:01:47 +0200
committerAlex Deucher <alexander.deucher@amd.com>2020-08-10 23:26:52 +0200
commit8d0717f422255513ae1afab2ea0b75ba9f1512a9 (patch)
tree39771fe1dd8667767513b96d8e486ee9776292b9 /drivers
parentdrm/amd/powerplay: correct Vega20 cached smu feature state (diff)
downloadlinux-8d0717f422255513ae1afab2ea0b75ba9f1512a9.tar.xz
linux-8d0717f422255513ae1afab2ea0b75ba9f1512a9.zip
drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading
The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to assume the bootup state in SMU based on the dpm status. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 303e764af11a..c9f402edc0d6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1645,12 +1645,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
data->uvd_power_gated = true;
data->vce_power_gated = true;
-
- if (data->smu_features[GNLD_DPM_UVD].enabled)
- data->uvd_power_gated = false;
-
- if (data->smu_features[GNLD_DPM_VCE].enabled)
- data->vce_power_gated = false;
}
static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)