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| author | Abel Vesa <abel.vesa@linaro.org> | 2024-10-21 15:53:28 +0200 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2024-10-21 20:03:25 +0200 |
| commit | 16fde3e076775d3b51f48d44d050746fbc9d638e (patch) | |
| tree | 6cf5af5b978b18b775219a30c6bd2fcc411f232d /fs/smb/server/transport_ipc.c | |
| parent | phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock check (diff) | |
| download | linux-16fde3e076775d3b51f48d44d050746fbc9d638e.tar.xz linux-16fde3e076775d3b51f48d44d050746fbc9d638e.zip | |
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix X1E80100 resets entries
The PCIe 6a PHY is actually Gen4 4-lanes capable. So the gen4x4 compatible
describes it. But according to the schema, currently the gen4x4 compatible
doesn't require both PHY and PHY-nocsr resets, while the HW does. So fix
that by adding the gen4x4 compatible alongside the gen4x2 one for the
resets description.
Fixes: 0c5f4d23f776 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x4")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202410182029.n2zPkuGx-lkp@intel.com/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241021-phy-qcom-qmp-pcie-fix-x1e80100-gen4x4-resets-v3-1-1918c46fc37c@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'fs/smb/server/transport_ipc.c')
0 files changed, 0 insertions, 0 deletions