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| author | Herve Codina <herve.codina@bootlin.com> | 2024-08-08 09:11:00 +0200 |
|---|---|---|
| committer | Christophe Leroy <christophe.leroy@csgroup.eu> | 2024-09-03 07:49:18 +0200 |
| commit | a0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3 (patch) | |
| tree | 38919a8e688878c5b25288b3f5293c8644d8578d /include/dt-bindings/soc | |
| parent | soc: fsl: cpm1: tsa: Add missing spinlock comment (diff) | |
| download | linux-a0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3.tar.xz linux-a0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3.zip | |
dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Diffstat (limited to 'include/dt-bindings/soc')
| -rw-r--r-- | include/dt-bindings/soc/qe-fsl,tsa.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/dt-bindings/soc/qe-fsl,tsa.h b/include/dt-bindings/soc/qe-fsl,tsa.h new file mode 100644 index 000000000000..3cf3df9c0968 --- /dev/null +++ b/include/dt-bindings/soc/qe-fsl,tsa.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_SOC_FSL_QE_TSA_H +#define __DT_BINDINGS_SOC_FSL_QE_TSA_H + +#define FSL_QE_TSA_NU 0 +#define FSL_QE_TSA_UCC1 1 +#define FSL_QE_TSA_UCC2 2 +#define FSL_QE_TSA_UCC3 3 +#define FSL_QE_TSA_UCC4 4 +#define FSL_QE_TSA_UCC5 5 + +#endif |