diff options
| author | Taniya Das <quic_tdas@quicinc.com> | 2023-05-24 16:06:54 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-25 06:43:04 +0200 |
| commit | 1e910b2ba0edd639cc89b5495a3a832b28f77c7f (patch) | |
| tree | 1432ca54bd48cda12893dd98de4e0cf958c751f7 /include/dt-bindings | |
| parent | Linux 6.4-rc1 (diff) | |
| download | linux-1e910b2ba0edd639cc89b5495a3a832b28f77c7f.tar.xz linux-1e910b2ba0edd639cc89b5495a3a832b28f77c7f.zip | |
dt-bindings: clock: qcom: Add SM8450 video clock controller
Add device tree bindings for the video clock controller on Qualcomm
SM8450 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/qcom,sm8450-videocc.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h new file mode 100644 index 000000000000..9d795adfe4eb --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK 0 +#define VIDEO_CC_MVS0_CLK_SRC 1 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 2 +#define VIDEO_CC_MVS0C_CLK 3 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS1_CLK 5 +#define VIDEO_CC_MVS1_CLK_SRC 6 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS1C_CLK 8 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 +#define VIDEO_CC_PLL0 10 +#define VIDEO_CC_PLL1 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif |