diff options
| author | Jason Cooper <jason@lakedaemon.net> | 2014-09-14 09:53:39 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-09-14 09:53:39 +0200 |
| commit | ce92bfe88ba38e76371feb93307125fac3f800f0 (patch) | |
| tree | a10bca9849e16830a846dcabe6bcefcc4a8fbe36 /include | |
| parent | Merge branch 'irqchip/hip04' into irqchip/core (diff) | |
| parent | irqchip: gic: Preserve gic V2 bypass bits in cpu ctrl register (diff) | |
| download | linux-ce92bfe88ba38e76371feb93307125fac3f800f0.tar.xz linux-ce92bfe88ba38e76371feb93307125fac3f800f0.zip | |
Merge branch 'irqchip/gic' into irqchip/core
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/arm-gic.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 45e2d8c15bd2..13eed92c7d24 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -21,7 +21,11 @@ #define GIC_CPU_ACTIVEPRIO 0xd0 #define GIC_CPU_IDENT 0xfc +#define GICC_ENABLE 0x1 +#define GICC_INT_PRI_THRESHOLD 0xf0 #define GICC_IAR_INT_ID_MASK 0x3ff +#define GICC_INT_SPURIOUS 1023 +#define GICC_DIS_BYPASS_MASK 0x1e0 #define GIC_DIST_CTRL 0x000 #define GIC_DIST_CTR 0x004 @@ -39,6 +43,18 @@ #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 #define GIC_DIST_SGI_PENDING_SET 0xf20 +#define GICD_ENABLE 0x1 +#define GICD_DISABLE 0x0 +#define GICD_INT_ACTLOW_LVLTRIG 0x0 +#define GICD_INT_EN_CLR_X32 0xffffffff +#define GICD_INT_EN_SET_SGI 0x0000ffff +#define GICD_INT_EN_CLR_PPI 0xffff0000 +#define GICD_INT_DEF_PRI 0xa0 +#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ + (GICD_INT_DEF_PRI << 16) |\ + (GICD_INT_DEF_PRI << 8) |\ + GICD_INT_DEF_PRI) + #define GICH_HCR 0x0 #define GICH_VTR 0x4 #define GICH_VMCR 0x8 |