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| author | Koji Matsuoka <koji.matsuoka.xm@renesas.com> | 2016-06-28 09:33:45 +0200 |
|---|---|---|
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2016-11-15 00:44:51 +0100 |
| commit | 85e8f8d175caa6a39f4c4e11dd4d0ab038f43324 (patch) | |
| tree | 0d6f6e136f0c25b40164877e6aa6d43cf8af94e0 /mm/page_isolation.c | |
| parent | drm: rcar-du: Fix H/V sync signal polarity configuration (diff) | |
| download | linux-85e8f8d175caa6a39f4c4e11dd4d0ab038f43324.tar.xz linux-85e8f8d175caa6a39f4c4e11dd4d0ab038f43324.zip | |
drm: rcar-du: Fix LVDS start sequence on Gen3
According to the latest revision of the datasheet, the LVDS I/O pins
must be enabled before starting the PLL. Fix it.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'mm/page_isolation.c')
0 files changed, 0 insertions, 0 deletions