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authorMiquel Raynal <miquel.raynal@bootlin.com>2019-07-31 14:21:21 +0200
committerKishon Vijay Abraham I <kishon@ti.com>2019-08-27 08:07:09 +0200
commit0c79cf1f486135929f4370b6d919be0facdc1c8e (patch)
treeb8ec5962bc102a3d97b25a87f261414072558d08 /mm/percpu-stats.c
parentdt-bindings: phy: Add Marvell COMPHY clocks (diff)
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dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
Armada CP110 PCIe controller can have from one to four PHYs for configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the phys and phy-names properties in the bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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