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author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2024-02-20 08:00:07 +0100 |
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committer | Paolo Abeni <pabeni@redhat.com> | 2024-02-22 09:53:54 +0100 |
commit | 3489182b11d35f1944c1245fc9c4867cf622c50f (patch) | |
tree | 302b55140828897b4db04bd5c3be3e7eaedacd01 /scripts | |
parent | Merge branch 'ioam6-fix-write-to-cloned-skb-s' (diff) | |
download | linux-3489182b11d35f1944c1245fc9c4867cf622c50f.tar.xz linux-3489182b11d35f1944c1245fc9c4867cf622c50f.zip |
net: phy: realtek: Fix rtl8211f_config_init() for RTL8211F(D)(I)-VD-CG PHY
Commit bb726b753f75 ("net: phy: realtek: add support for
RTL8211F(D)(I)-VD-CG") extended support of the driver from the existing
support for RTL8211F(D)(I)-CG PHY to the newer RTL8211F(D)(I)-VD-CG PHY.
While that commit indicated that the RTL8211F_PHYCR2 register is not
supported by the "VD-CG" PHY model and therefore updated the corresponding
section in rtl8211f_config_init() to be invoked conditionally, the call to
"genphy_soft_reset()" was left as-is, when it should have also been invoked
conditionally. This is because the call to "genphy_soft_reset()" was first
introduced by the commit 0a4355c2b7f8 ("net: phy: realtek: add dt property
to disable CLKOUT clock") since the RTL8211F guide indicates that a PHY
reset should be issued after setting bits in the PHYCR2 register.
As the PHYCR2 register is not applicable to the "VD-CG" PHY model, fix the
rtl8211f_config_init() function by invoking "genphy_soft_reset()"
conditionally based on the presence of the "PHYCR2" register.
Fixes: bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/20240220070007.968762-1-s-vadapalli@ti.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions