diff options
| author | Ben Zhang <benzh@chromium.org> | 2015-10-20 01:49:05 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2015-10-22 18:17:38 +0200 |
| commit | c86ba612bdba4d267ce5aad30ff10b4d994e2b33 (patch) | |
| tree | 6174af7fb15a07fea2b581a9f2b5620379ad0794 /sound/soc/codecs/nau8825.h | |
| parent | ASoC: nau8825: add acpi match ID (diff) | |
| download | linux-c86ba612bdba4d267ce5aad30ff10b4d994e2b33.tar.xz linux-c86ba612bdba4d267ce5aad30ff10b4d994e2b33.zip | |
ASoC: nau8825: Add FLL configuration
snd_soc_codec_driver.set_pll is implemented to configure the FLL.
The codec internal SYSCLK can be from either the MCLK pin directly,
or the FLL. This is configured by snd_soc_codec_driver.set_pll.
Signed-off-by: Ben Zhang <benzh@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/nau8825.h')
| -rw-r--r-- | sound/soc/codecs/nau8825.h | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 8774923502b4..dff8edb83bfd 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -101,13 +101,31 @@ #define NAU8825_ENABLE_SAR_SFT 1 /* CLK_DIVIDER (0x3) */ -#define NAU8825_CLK_SRC_SFT 15 -#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) -#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) -#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_SRC_SFT 15 +#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) + +/* FLL1 (0x04) */ +#define NAU8825_FLL_RATIO_MASK (0x7f << 0) + +/* FLL3 (0x06) */ +#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) + +/* FLL4 (0x07) */ +#define NAU8825_FLL_REF_DIV_MASK (0x3 << 10) + +/* FLL5 (0x08) */ +#define NAU8825_FLL_FILTER_SW_MASK (0x1 << 14) /* FLL6 (0x9) */ -#define NAU8825_DCO_EN (1 << 15) +#define NAU8825_DCO_EN_MASK (0x1 << 15) +#define NAU8825_DCO_EN (0x1 << 15) +#define NAU8825_DCO_DIS (0x0 << 15) +#define NAU8825_SDM_EN_MASK (0x1 << 14) +#define NAU8825_SDM_EN (0x1 << 14) +#define NAU8825_SDM_DIS (0x0 << 14) /* HSD_CTRL (0xc) */ #define NAU8825_HSD_AUTO_MODE (1 << 6) |